Method and system for controlling a mixed array of point-of-load regulators through a bus translator
View Patent ↗A power control system comprises at least one point-of-load (POL) regulator adapted to provide an output voltage to a corresponding load and a system controller operatively connected to the at least one POL regulator via a data bus and adapted to send a first data message in a first format to the at least one POL regulator via the data bus. A bus translator is interposed along the data bus between the at least one POL regulator and the system controller. The bus translator converts the first data message from the first format to a second format that is compatible with the at least one POL regulator. The bus translator is adapted for bi-directional operation to convert a second data message communicated from the at least one POL regulator in the second format to the first format compatible with the system controller. The first and second data formats may comprise either a digital data format or an analog data format. The bus translator may further include a phase-locked loop circuit adapted to synchronize operation of the bus translator to a detected data rate of the data bus.
1. A power control system comprising:
at least one point-of-load (POL) regulator comprising a POL controller and a power conversion circuit adapted to provide an output voltage to a corresponding load;
a system controller operatively connected to the POL controller via a data bus and adapted to send a first data message in a first format to the POL controller via the data bus; and
a bus translator interposed along the data bus between the POL controller and the system controller, the bus translator converting the first data message from the first format to a second format that is compatible with the POL controller;
wherein the POL controller uses at least a portion of the first data message in the second format to produce, via the power conversion circuit, the output voltage.
2. The power control system of claim 1 , wherein the data bus further comprises a serial data bus.
3. The power control system of claim 1 , wherein the bus translator is adapted for bi-directional operation to convert a second data message communicated from the POL controller in the second format to the first format compatible with the system controller.
4. The power control system of claim 3 , wherein the second data message further comprises status monitoring data from the POL controller.
5. The power control system of claim 1 , wherein said second format comprises a digital data format.
6. The power control system of claim 1 , wherein said second format comprises an analog data format.
7. The power control system of claim 1 , wherein the bus translator further comprises a phase synchronization circuit adapted to synchronize operation of the bus translator to a detected data rate of the data bus.
8. The power control system of claim 7 , wherein the phase synchronization circuit further comprises a phase-locked looped circuit.
9. The power control system of claim 7 , wherein the phase synchronization circuit is driven by external event signals.
10. The power control system of claim 1 , wherein the bus translator further comprises a memory unit containing instructions for converting between the first and second formats.
11. The power control system of claim 1 , wherein the first data message further comprises programming data for the at least one POL regulator.
12. A method of controlling a power control system, comprising:
generating initial-configuration data intended for at least one point of load (POL) regulator, the at least one POL regulator comprising a POL controller and a power conversion circuit adapted to provide an output voltage to a corresponding load;
translating the initial-configuration data from a first format to a second format that is compatible with the POL controller;
propagating the translated initial-configuration data to the POL controller; and
operating the POL controller to control a characteristic of the output voltage in accordance with at least a portion of the translated initial-configuration data.
13. The method of claim 12 , further comprising:
generating a data message at the at least one POL regulator intended for a power system controller;
translating the data message from the second format to the first format that is compatible with the power system controller;
propagating the translated data message to the power system controller; and
operating the power control system in accordance with the translated data message.
14. The method of claim 12 , wherein said second format comprises a digital data format.
15. The method of claim 12 , wherein said second format comprises an analog data format.
16. A bus translator for use in a power control system comprising at least one point-of-load (POL) regulator adapted to provide an output voltage to a corresponding load, and a system controller operatively connected to the at least one POL regulator and adapted to send a first data message in a first format to the at least one POL regulator, the bus translator being interposed between a POL controller of the at least one POL regulator and the system controller, the bus translator translating the first data message from the first format to a second format that is compatible with the POL controller and propagating the translated first data message POL controller, wherein the POL controller uses at least a portion of the translated first data message to produce, via a power conversion circuit of the at least one POL regulator, the output voltage.
17. The bus translator of claim 16 , further adapted for bi-directional operation to convert a second data message communicated from the at least one POL regulator in the second format to the first format compatible with the system controller.
18. The bus translator of claim 16 , wherein said second format comprises a digital data format.
19. The bus translator of claim 16 , wherein said second format comprises an analog data format.
20. The bus translator of claim 16 , further comprising a phase synchronization circuit adapted to synchronize operation to a detected data rate of the data bus.
21. The bus translator of claim 16 , further comprising a memory unit containing stored instructions for converting between the first and second formats.