Field effect transistor with a fin structure

1. A field effect transistor with a fin structure, comprising:

a first and a second source/drain region;

a body region formed within the fin structure and between the first and the second source/drain region;

a first metallically conductive region formed within a part of the first source/drain region, the first metallically conductive region being adjacent to the body region or to a first lightly doped region disposed between the body region and the first source/drain region; and

a first current ballasting region formed within a part of the first source/drain region; and

a first source/drain contact region formed within a part of the first source/drain region;

wherein the first current ballasting region is disposed such that it separates the first metallically conductive region from the first source/drain contact region.

2. The field effect transistor as claimed in 1 , wherein the first source/drain contact region includes a metallically conductive material.

3. The field effect transistor as claimed in 1 , wherein the first source/drain contact region is formed as a fully silicided region.

4. The field effect transistor as claimed in 1 , wherein the first source/drain contact region is formed as a silicided region in a surface area of the first source/drain region.

5. The field effect transistor as claimed in 1 , further comprising:

a second metallically conductive region formed within a part of the second source/drain region.

6. The field effect transistor as claimed in 5 , wherein at least one of the first metallically conductive region and the second metallically conductive region comprises silicide material.

7. The field effect transistor as claimed in 6 , wherein at least one of the first metallically conductive region and the second metallically conductive region is formed as a fully silicided region.

8. The field effect transistor as claimed in 6 , wherein the first metallically conductive region and the second metallically conductive region are formed in surface areas of the first and second source/drain regions, respectively.

9. The field effect transistor as claimed in 5 , wherein the second metallically conductive region is formed within the entirety of the second source/drain region.

10. The field effect transistor as claimed in 5 , further comprising a second current ballasting region formed within a part of the second source/drain region.

11. The field effect transistor as claimed in 10 , wherein the second metallically conductive layer is adjacent to the body region or to a second lightly doped region disposed between the body region and the second source/drain region.

12. The field effect transistor as claimed in 11 , further comprising:

a second source/drain contact region formed within a part of the second source/drain region;

wherein the second current ballasting region is disposed such that it separates the second metallically conductive region from the second source/drain contact region.

13. The field effect transistor as claimed in 12 , wherein the second source/drain contact region includes a metallically conductive material.

14. The field effect transistor as claimed in 12 , wherein the second source/drain contact region is formed as a fully silicided region.

15. The field effect transistor as claimed in 12 , wherein the second source/drain contact region is formed as a silicided region in a surface area of the second source/drain region.

16. The field effect transistor as claimed in 1 , further comprising:

a gate region disposed on or above the body region.

17. The field effect transistor as claimed in 16 , further comprising:

a suicide layer disposed on the gate region.

18. The field effect transistor as claimed in 16 , wherein the gate region comprises a polysilicon gate, the polysilicon gate being partially silicided or fully silicided.

19. The field effect transistor as claimed in 18 , the gate region further comprising a metal gate, the polysilicon gate being disposed on or above the metal gate.

20. The field effect transistor as claimed in 16 , wherein the fin structure comprises silicon material.

21. The field effect transistor as claimed in 20 , wherein the fin structure is disposed on an electrically insulating layer.

22. The field effect transistor as claimed in 1 , further comprising a second lightly doped region between the body region and the second source/drain region, wherein at least one of the first lightly doped region and the second lightly doped region is an extension region.

23. The field effect transistor as claimed in 1 , further comprising a second lightly doped region between the body region and the second source/drain region, wherein at least one of the first lightly doped region and the second lightly doped region comprises a halo region.

24. A method of fabricating a field effect transistor, comprising

forming a first and a second source/drain region;

forming a body region within a fin structure of the field effect transistor and between the first and the second source/drain region;

forming a gate region on or above the body region;

forming a first metallically conductive region within a part of the first source/drain region, the first metallically conductive region being adjacent to the body region or to a first lightly doped region disposed between the body region and the first source/drain region; and

forming a first current ballasting region within a part of the first source/drain region; and

forming a first source/drain contact region within a part of the first source/drain region;

wherein the first current ballasting region is disposed such that it separates the first metallically conductive region from the first source/drain contact region.

25. A field effect transistor with a fin structure, comprising:

a first and a second source/drain region;

a body region formed within the fin structure and between the first and the second source/drain region;

a first current ballasting region formed within a part of the first source/drain region, the first current ballasting region being adjacent to the body region or to a first lightly doped region disposed between the body region and the first source/drain region; and

a first metallically conductive region formed within a part of the first source/drain region, the first metallically conductive region being adjacent to the first current ballasting region;

wherein the first metallically conductive region is formed as a fully silicided region.

26. The field effect transistor as claimed in 25 , further comprising:

a second metallically conductive region formed within a part of the second source/drain region.

27. The field effect transistor as claimed in 26 , wherein the second metallically conductive region comprises silicide material.

28. The field effect transistor as claimed in 27 , wherein the second metallically conductive region is formed as a fully silicided region.

29. The field effect transistor as claimed in 26 , wherein the second metallically conductive region is formed within the entirety of the second source/drain region.

30. A method of fabricating a field effect transistor, comprising:

forming a first and a second source/drain region;

forming a body region within a fin structure of the field effect transistor and between the first and the second source/drain region;

forming a first current ballasting region within a part of the first source/drain region, the first current ballasting region being adjacent to the body region or to a first lightly doped region disposed between the body region and the first source/drain region; and

forming a first metallically conductive region within a part of the first source/drain region, the first metallically conductive region being adjacent to the first current ballasting region;

wherein the first metallically conductive region is formed as a fully silicided region.