Refresh period adjustment technique for dynamic random access memories (DRAM) and integrated circuit devices incorporating embedded DRAM
View Patent ↗A DRAM refresh period adjustment technique based on the retention time of one or more unused memory cell(s) having characteristics very similar to the characteristics of the memory cell(s) with the shortest retention time used in the DRAM array. In a particular implementation of the technique of the present invention, the refresh period of a DRAM array is adjusted through the use of one or more of the DRAM bits that fail to meet the retention time requirement and have, therefore, been replaced by redundant DRAM bits. These replaced bits are then used to indicate the refresh period for the DRAM is the maximum it can be for the DRAM under then current operating conditions.
1. A DRAM array refresh period adjustment method comprising:
determining a retention time of at least some of said DRAM array bits;
replacing those DRAM array bits with the shortest retention time with spare bits; and
establishing as indicator bits, one or more of those replaced DRAM array bits having a somewhat shorter retention time than any DRAM array bits not replaced.
2. The method of claim 1 further comprising:
refreshing said DRAM array bits in accordance with a predetermined refresh time period;
determining a state of said indicator bits; and
increasing said refresh time period of said DRAM array bits to an increased refresh time period if said indicator bits have maintained their data state;
decreasing said refresh time period of said DRAM array bits to a decreased refresh time period if said indicator bits have not maintained their data state.
3. The method of claim 2 further comprising:
subsequently refreshing said DRAM array bits in accordance with either said increased or decreased refresh time period.
4. The method of claim 2 wherein said step of refreshing said DRAM array bits further comprises:
initializing a refresh timer;
setting said refresh timer to said predetermined refresh time period; and
monitoring said refresh timer to determine when said predetermined refresh time period has elapsed.
5. A DRAM array refresh period adjustment method comprising:
determining a retention time of at least some of said DRAM array bits;
replacing those DRAM array bits with the shortest retention time with spare bits; and
establishing as indicator bits, one or more of those replaced DRAM array bits having a substantially equal retention time to the not replaced DRAM array bits with the shortest retention time.
6. The method of claim 5 further comprising:
refreshing said DRAM array bits in accordance with a first predetermined refresh time period;
initializing a second longer predetermined refresh time period substantially concurrently with an initialization of said first predetermined refresh time period;
determining a state of said indicator bits upon elapse of said second predetermined refresh time period; and
increasing said first and second predetermined refresh time periods of said DRAM array bits to an increased refresh time period if said indicator bits have maintained their data state;
decreasing said first and second predetermined refresh time periods of said DRAM array bits to a decreased refresh time period if said indicator bits have not maintained their data state.
7. The method of claim 6 further comprising:
subsequently refreshing said DRAM array bits in accordance with either said increased or decreased refresh time period.
8. The method of claim 7 wherein said step of refreshing said DRAM array bits further comprises:
initializing standard and long refresh timers;
setting said standard refresh timer to said first predetermined refresh time period;
setting said long refresh timer to said second longer predetermined refresh time period; and
monitoring said standard and long refresh timers to determine when said respective first and second predetermined refresh time periods have elapsed.
9. A DRAM array refresh period adjustment method comprising:
replacing selected ones of said DRAM array bits having a shortest retention time with spare DRAM array bits;
utilizing at least one or more of said replaced DRAM bits having a retention time similar to the shortest retention time of said DRAM array bits not replaced as one or more indicator bits; and
setting a refresh time period for said DRAM array based on said retention time of said one or more indicator bits.
10. The method of claim 9 further comprising:
selecting said one or more indicator bits as those with a somewhat shorter retention time than said DRAM array bits not replaced.
11. The method of claim 9 further comprising:
selecting said one or more indicator bits as those with a substantially similar retention time as said DRAM array bits not replaced.