Patent Assignment
Reel/Frame 029550/0782
Assignment of Assignor's Interest
Recorded: 2012-12-31
Pages: 10
Assignor
PROMOS TECHNOLOGIES PTE. LTD.
Executed: 2012-12-11
Assignee
PROMOS TECHNOLOGIES, INC.
3F., NO. 19-1, LI HSIN RD., SCIENCE BASED INDUSTRIAL PARK, HSINCHU, TAIWAN
Covered Properties
(32)
Data Sorting in Memories
Multistage Parallel-to-Serial Conversion of Read Data in Memories, with the First Serial Bit Skipping at Least One Stage
High-Speed, Low-Power Input Buffer for Integrated Circuit Devices
Wide Window Clock Scheme for Loading Output Fifo Registers
Reducing Nitrogen Concentration with in-Situ Steam Generation
Fabrication of Semiconductor Device Exhibiting Reduced Dielectric Loss in Isolation Trenches
Patent:
7,355,239 →
Application:
11/514,743 →
Refresh Period Adjustment Technique for Dynamic Random Access Memories (Dram) and Integrated Circuit Devices Incorporating Embedded Dram
Circuit and Technique for Adjusting and Accurately Controlling Clock Duty Cycles in Integrated Circuit Devices
High-Speed, Low-Power Input Buffer for Integrated Circuit Devices
Integrated Circuits with Substrate Protrusions, Including (but Not Limited to) Floating Gate Memories
Use of Multiple Voltage Controlled Delay Lines for Precise Alignment and Duty Cycle Control of the Data Output of a Ddr Memory Device
Automatic Duty Cycle Correction Circuit with Programmable Duty Cycle Target
Non-Volatile Memory Devices with Charge Storage Regions
Methods for Inspecting and Optionally Reworking Summed Photolithography Patterns Resulting from Plurally-Overlaid Patterning Steps During Mass Production of Semiconductor Devices
N-Bit Shift Register Controller
Nonvolatile Memories with Laterally Recessed Charge-Trapping Dielectric
Using Differential Data Strobes in Non-Differential Mode to Enhance Data Capture Window
Twin Cell Architecture for Integrated Circuit Dynamic Random Access Memory (Dram) Devices and Those Devices Incorporating Embedded Dram
Multi-Bank Block Architecture for Integrated Circuit Memory Devices Having Non-Shared Sense Amplifier Bands Between Banks
Asymetric Data Path Position and Delays Technique Enabling High Speed Access in Integrated Circuit Memory Devices
Low Skew Differential Amplifier Using Tail Voltage Reference and Tail Feedback
Photolithography with Optical Masks Having More Transparent Features Surrounded by Less Transparent Features
Method of Repairing Deep Subsurface Defects in a Silicon Substrate That Includes Diffusing Negatively Charged Ions into the Substrate from a Sacrificial Oxide Layer
Shielding of Datalines with Physical Placement Based on Time Staggered Access
Nonvolatile Memories with Tunnel Dielectric with Chlorine
Integrated Circuits with Substrate Protrusions, Including (but Not Limited to) Floating Gate Memories
Fabrication of Integrated Circuits with Isolation Trenches
High Capacitive Load and Noise Tolerant System and Method for Controlling the Drive Strength of Output Drivers in Integrated Circuit Devices
Configurable Architecture Hybrid Analog/Digital Delay Locked Loop (Dll) and Technique with Fast Open Loop Digital Locking for Integrated Circuit Devices
Dual Bit Line Precharge Architecture and Method for Low Power Dynamic Random Access Memory (Dram) Integrated Circuit Devices and Devices Incorporating Embedded Dram
Dual Bit Line Precharge Architecture and Method for Low Power Dynamic Random Access Memory (Dram) Integrated Circuit Devices and Devices Incorporating Embedded Dram
Application:
12/834,721 →
Publication:
US 2012/0008445
Semiconductor Devices with Gate Electrodes and with Monocrystalline Silicon Regions That Contain Atoms of Nitrogen and One or More of Chlorine, Bromine, Sulfur, Fluorine, or Phosphorus
Related Assignments
(1)
Other recorded transfers of the patents in this record — the chain of ownership.