N-bit shift register controller
View Patent ↗A column repair circuit uses a system of circuits that automatically stops the shifting of register contents independently of the number of bits to be shifted. The circuit is only dependent on the number of bits in a column address repair block. By adding shift register positions to one end of each shift register chain, a dedicated block of bits is used to detect the end of the shift chain without explicitly knowing the length of the chain. The shift register positions provide a hard-programmed code that can be used to stop the shifting of data automatically. The shift register positions also provide a space for hard-programmed code bits that can be examined to determine when the shift process ends. A shift chain can be controlled with a controller so long as the information is organized into groups of ‘k’ bits. The controller only requires information regarding the value of the number ‘k’ and the pre-programmed stop code in order to control any number of bits in a shift chain.
1. A self-controlled shift register circuit comprising N number of bits to be shifted, which are controlled by the state of an M-bit counter, wherein M is independent of the number N, wherein a set number of bits K is used to detect a condition for termination of the shifting of the N number of bits.
2. The self-controlled shift register circuit of claim 1 wherein the length of the entire self-controlled shift register comprises N+K.
3. The self-controlled shift register circuit of claim 1 wherein shifting begins each time a single input signal pulses.
4. The self-controlled shift register circuit of claim 1 wherein no shifting occurs until a single input signal pulses.
5. A self-controlled shift register circuit comprising N number of bits to be shifted, which are controlled by the state of an M-bit counter, wherein M is independent of the number N, and further comprising a hard-programmed code of K bits that is shifted through the register.
6. The self-controlled shift register circuit of claim 5 wherein the hard-programmed code of K bits comprises an invalid code.
7. The self-controlled shift register circuit of claim 5 wherein shifting begins each time a single input signal pulses.
8. The self-controlled shift register circuit of claim 5 wherein no shifting occurs until a single input signal pulses.