Using differential data strobes in non-differential mode to enhance data capture window
View Patent ↗A data capture circuit includes strobes that track input data even when conditions arise that cause the differences in skew from interpreting data state ones and zeros. This is accomplished whether these skews arise from reference voltage variation, data pattern loading, power supply droop, process variations within the chip itself, or other causes. The differential input strobes of the data capture circuit are input into individual input buffers, each compared against a reference voltage individually, as well as a data input pin. The outputs from these buffers are maintained separate from each other all the way to the point where the input data is latched. In latching the input data, data ones are latched entirely based on input signals derived from a rising edge (both strobes and data), and zeros are latched entirely based on input signals derived from a falling edge (both strobes and data).
1. A data capture circuit comprising:
a differential strobe signal including first and second single-ended strobe signals;
a single-ended data signal;
a reference voltage;
a first differential amplifier having a first input for receiving the first single-ended strobe signal, a second input for receiving the reference voltage, and an output;
a second differential amplifier having a first input for receiving the single-ended data signal, a second input for receiving the reference voltage, and an output;
a third differential amplifier having a first input for receiving the second single-ended strobe signal, a second input for receiving the reference voltage, and an output;
a first dual-cascode circuit having first and second P-channel transistors and first and second N-channel transistors with their respective current paths in cascode connection, a gate of the first P-channel transistor being coupled to the output of the first differential amplifier, a gate of the second P-channel transistor and the first N-channel transistor being coupled together and to the output of the second differential amplifier, and a gate of the second N-channel transistor being coupled to the output of the third differential amplifier, and an output for providing a rising data signal; and
a second dual-cascode circuit having first and second P-channel transistors and first and second N-channel transistors with their respective current paths in cascade connection, a gate of the first P-channel transistor being coupled to the output of the first differential amplifier, a gate of the second P-channel transistor and the first N-channel transistor being coupled together and to the output of the second differential amplifier, and a gate of the second N-channel transistor being coupled to the output of the third differential amplifier, and an output for providing a falling data signal,
wherein the rising and falling data signals are subsequently processed to provide falling edge zero, falling edge one, rising edge zero, and rising edge one data signals.
2. The data capture circuit of claim 1 further comprising:
a rising data latch circuit having an input for receiving the rising data signal and an output; and
a falling data latch circuit having an input for receiving the falling data signal and an output.
3. The data capture circuit of claim 2 further comprising:
a first shift register chain coupled to the rising data latch circuit for providing the rising edge zero and rising edge one data signals; and
a second shift register chain coupled to the falling data latch circuit for providing the falling edge zero and falling edge one data signals.
4. The data capture circuit of claim 3 further comprising a break before make shift register control circuit having a first input coupled to the output of first differential amplifier, a second input coupled to the output of the third differential amplifier, and an output for providing a plurality of control signals to the first shift register chain and to the second shift register chain.
5. The data capture circuit of claim 1 further comprising selection circuitry for selecting between a non-differential strobe mode and a differential strobe mode.
6. The data capture circuit of claim 1 further comprising at least one tunable capacitor for adjusting the delay of a signal path associated with the first, second, or third differential amplifier outputs.
7. A data capture circuit comprising:
a differential strobe signal including first and second single-ended strobe signals;
a single-ended data signal;
a reference voltage;
a first differential amplifier having a first input for receiving the first single-ended strobe signal, a second input for receiving the reference voltage, and an output;
a second differential amplifier having a first input for receiving the single-ended data signal, a second input for receiving the reference voltage, and an output;
a third differential amplifier having a first input for receiving the second single-ended strobe signal, a second input for receiving the reference voltage, and an output;
a first dual-cascade circuit having first and second P-channel transistors and first and second N-channel transistors with their respective current paths in cascode connection, a gate of the first P-channel transistor being coupled to the output of the first differential amplifier, a gate of the second P-channel transistor and the first N-channel transistor being coupled together and to the output of the second differential amplifier, and a gate of the second N-channel transistor being coupled to the output of the third differential amplifier, and an output for providing a rising data signal; and
a second dual-cascode circuit having first and second P-channel transistors and first and second N-channel transistors with their respective current paths in cascade connection, a gate of the first P-channel transistor being coupled to the output of the first differential amplifier, a gate of the second P-channel transistor and the first N-channel transistor being coupled together and to the output of the second differential amplifier, and a gate of the second N-channel transistor being coupled to the output of the third differential amplifier, and an output for providing a falling data signal,
wherein the rising and falling data signals are subsequently processed to provide captured data signals such that an initial setup time period between at least one of the strobe signals and the data signal is maintained during subsequent processing.
8. The data capture circuit of claim 7 wherein the captured data signals comprise falling edge zero, falling edge one, rising edge zero, and rising edge one data signals.
9. The data capture circuit of claim 7 further comprising a plurality of tunable capacitors.
10. The data capture circuit of claim 7 further comprising a shift register chain having a plurality of control inputs for preventing data run-through.