Methods for inspecting and optionally reworking summed photolithography patterns resulting from plurally-overlaid patterning steps during mass production of semiconductor devices
View Patent ↗A batch of wafers is temporarily stalled during a Double Pattern Technology (DPT) process before a temporary representation of a second of to-be-overlaid patterns is permanently combined with a first of the patterns. Sampled ones of the stalled wafers are inspected to determine if sufficiently close alignment is present between the two patterns. If excessive misalignment is detected (e.g., by SEM microscopy), the second but still temporary pattern representation is erased from all wafers of the batch and the batch is routed for rework and corrected reestablishment of the temporary representation of the second of to-be-overlaid patterns.
1. An in-process plurality of patterned wafers wherein:
(a) each patterned wafer has exposed thereon, a temporary patterns summing layer (TPSL) containing a first set of patterned features composed of a first material and representing a first of overlaid photomask patterns and containing a second set of patterned features composed of a different second material and representing a second of the overlaid photomask patterns, the TPSL being for performing further patterning of the patterned wafer in subsequent processing; and wherein
(b) at least one of the in-process patterned wafers has had its exposed TPSL inspected by way of one or more preselected measurement techniques to verify that the first and second sets of patterned features are positioned relative to at least one another in accordance with a predetermined spacing specification.
2. The in-process plurality of patterned wafers of claim 1 wherein:
(a) the temporary patterns summing layer (TPSL) of each patterned wafer includes an in-scribe test pattern configured for use by one or more of the preselected measurement techniques to verify that the first and second sets of patterned features are positioned relative to at least one another in accordance with the predetermined spacing specification.
3. The in-process plurality of patterned wafers of claim 1 wherein at least one of the first and second materials is a hard-mask material.
4. The in-process plurality of patterned wafers of claim 3 wherein at least one of the first and second materials comprises an oxide and/or a nitride and/or an oxynitride and/or a semiconductor and/or a refractory metal compound.
5. The in-process plurality of patterned wafers of claim 3 wherein at least one of the first and second materials comprises silicon oxide and/or silicon nitride and/or silicon oxynitride.
6. The in-process plurality of patterned wafers of claim 3 wherein at least one of the first and second materials comprises silicon.
7. The in-process plurality of patterned wafers of claim 3 wherein at least one of the first and second materials comprises a refractory metal compound.
8. The in-process plurality of patterned wafers of claim 1 wherein the patterned wafers are in the process which is for fabricating one or more integrated circuits from each wafer.
9. The in-process plurality of patterned wafers of claim 8 the TPSL is for defining patterns to be transferred into an underlying layer of the at least one of the in-process patterned wafers.
10. The in-process plurality of patterned wafers of claim 9 wherein the patterns defined using TPSL are to be transferred using an etch.