Timing variation characterization

1. A method comprising:

grouping cells with similar topological characteristics into a family of cells, the topological characteristics being defined in part by topological layouts of transistors in the respective cells in the family of cells; and

computing by a computer, data characterizing a relationship between a variability of delay and a magnitude of delay shared among the cells in the family of cells.

2. The method of claim 1 wherein the variability of delay comprises a standard deviation of the delay.

3. The method of claim 1 wherein the magnitude of delay comprises a mean delay.

4. The method of claim 1 wherein computing data characterizing variability of delay shared among a plurality of cells included in a family of cells comprises computing data characterizing variability of rise time delay shared among a plurality of cells included in a family of cells.

5. The method of claim 4 wherein the family of cells is defined by a topological layout of PMOS transistors in the cell.

6. The method of claim 1 wherein computing data characterizing variability of delay shared among a plurality of cells included in a family of cells comprises computing data characterizing variability of fall time delay shared among a plurality of cells included in a family of cells.

7. The method of claim 6 wherein the family of cells is defined by a topological layout of NMOS transistors in the cell.

8. The method of claim 1 , wherein the topological layout of transistors in the cell comprises a stack height of transistors in the cell.

9. The method of claim 1 , wherein the topological layout of transistors in the cell comprises a number of fingers per input in the cell.

10. The method of claim 1 , further comprising performing statistical timing analysis for a plurality of interconnected cells based on the computed data.

11. The method of claim 1 , further comprising determining a delay for each cell in the plurality of cells included in the family of cells.

12. The method of claim 11 , wherein the delay for each cell comprises a mean delay.

13. The method of claim 12 , further comprising computing a variation in delay for a particular cell included in the family of cells based on a ratio of the variability of delay for the family of cells and the determined mean delay for the particular cell.

14. The method of claim 13 , wherein the variability in delay comprises a standard deviation.

15. The method of claim 1 , wherein at least some of the data characterizing variability of delay shared among a plurality of cells included in a family of cells comprises a factor, f, such that a ratio of the variation of delay to the mean variation for a particular cell is approximately constant for the plurality of cells included in the family of cells.

16. The method of claim 1 , wherein the topological layout of the transistors is independent from the wiring of the transistors to form a gate.

17. The method of claim 1 , wherein a first cell in the family of cells performs a first logical operation and a second cell in the family of cells performs a second logical operation, the second logical operation being different from the first logical operation.

18. The method of claim 1 , wherein the computing data characterizing variability of delay shared among the plurality of cells included in the family of cells is performed for a plurality of families of cells, each family of the plurality of families of cells having a different topological layout.

19. A method comprising:

determining a mean delay for a cell;

retrieving a factor associated with variability of delay determined based on measurements associated with a representative cell having a similar topological layout as a second cell; and

calculating by a computer a variation of delay for the second cell based on the retrieved factor and the determined mean of the second cell.

20. A method for grouping cells into families, the method comprising:

determining a finger count representing a number of transistors arranged in a substrate in a parallel arrangement;

determining a stack count representing a number of transistors arranged in a substrate in a series arrangement; and

grouping by a computer cells into layout-based families of cells based on the determined finger count and determined stack count, wherein at least some of the layout-based families of cells include a first cell configured to perform a first logical function and a second cell configured to perform a second logical function, the first logical function being different than the second logical functions, wherein each family of cells shares a common delay characteristic.

21. The method of claim 20 , wherein the common delay characteristic comprises a variability of delay.

22. A computer program product tangibly embodied in a computer readable medium comprising instructions to cause a machine to:

compute data characterizing a relationship between a variability of delay and a maguitude of delay shared among a plurality of cells included in a family of cells,

wherein the plurality of cells included in the family of cells possess similar topological characteristics, the topological characteristics being defined in part by topological layouts of transistors in the respective cells in the family of cells.

23. The computer program product of claim 22 wherein the variability of delay comprises a standard deviation of the delay.

24. The computer program product of claim 22 wherein the magnitude of delay comprises a mean delay.

25. The computer program product of claim 22 wherein the instructions to cause the machine to compute data characterizing variability of delay shared among a plurality of cells included in a family of cells comprise instructions to cause a machine to compute data characterizing variability of rise time delay shared among a plurality of cells included in a family of cells, wherein the family of cells is defined by a topological layout of PMOS transistors in the cell.

26. The computer program product of claim 22 wherein the instructions to cause the machine to compute data characterizing variability of delay shared among a plurality of cells included in a family of cells comprise instructions to cause a machine to compute data characterizing variability of fall time delay shared among a plurality of cells included in a family of cells, wherein the family of cells is defined by a topological layout of NMOS transistors in the cell.

27. The computer program product of claim 22 , wherein the topological layout of transistors in the cell comprises:

a stack height of transistors in the cell; and

a number of fingers per input in the cell.

28. The computer program product of claim 22 , wherein at least some of the data characterizing variability of delay shared among a plurality of cells included in a family of cells comprises a factor, f, such that a ratio of the variation of delay to the mean variation for a particular cell is approximately constant for the plurality of cells included in the family of cells.

29. A computer program product tangibly embodied in a computer readable medium comprising instructions to cause a machine to:

determine a mean delay for a cell;

retrieve a factor associated with variability of delay determined based on measurements associated with a representative cell having a similar topological layout as a second cell; and

calculate a variation of delay for the second cell based on the retrieved factor and the determined mean of the second cell.