Method of reducing charging damage to integrated circuits during semiconductor manufacturing
View Patent ↗An integrated circuit die includes thereon a first device region, a second device region and a non-active region. A first implant mask, which covers the second device region and the non-active region, while exposing the first device region, is formed over the semiconductor substrate. Dopant species are implanted into the exposed semiconductor substrate within the first device region to form first doping regions therein. A second implant mask is formed over the semiconductor substrate. The second implant mask covers the first device region, while exposing the second device region and a portion of the non-active region. Dopant species are implanted into the exposed semiconductor substrate within the second device region to form second doping regions therein.
1. A method for reducing charging damage to integrated circuits during semiconductor manufacturing, comprising:
providing a semiconductor substrate comprising thereon a number of integrated circuit dies, said integrated circuit dies being separated from each other by scribe lanes surrounding each said integrated circuit die, wherein said semiconductor substrate comprises thereon a dielectric layer;
forming a mask over said dielectric layer, said mask comprising an interconnect opening and a dummy, non-interconnect opening, wherein said interconnect opening and said dummy, non-interconnect opening both are formed within each said integrated circuit die;
performing a plasma etching process to etch said dielectric layer through said interconnect opening and said dummy, non-interconnect openings of said mask, thereby forming an interconnect recessed trench and a dummy recessed trench in said dielectric layer; and
filling said interconnect recessed trench and said dummy recessed trench with conductive materials to form an interconnect feature and a dummy, non-interconnect feature, wherein said interconnect feature electrically connects to an underlying conductive layer, while said dummy, non-interconnect feature is floating or grounded to said semiconductor substrate;
wherein said dummy, non-interconnect opening increases an in-die shunt path current flow during said plasma etching process, thereby reducing charge damage to said integrated circuit dies.
2. The method according to claim 1 wherein an exposed surface area of said interconnect and dummy, non-interconnect openings is higher than 5% of a die area of each said integrated circuit die.
3. The method according to claim 1 wherein said mask comprises photoresist.
4. The method according to claim 1 wherein said interconnect recessed trench is a damascene opening.
5. The method according to claim 1 wherein said interconnect recessed trench is a contact hole.
6. The method according to claim 1 wherein said underlying conductive layer comprises metal wiring and diffusion region.