Electrically erasable programmable read-only memory cell and memory device
View Patent ↗A manufacturing method and a device of an EEPROM cell are provided. The method includes the following steps. First, a tunnel layer and an inter-gate dielectric layer are formed over a surface of a substrate respectively, and a doped region is formed in the substrate under the inter-gate dielectric layer and used as a control gate. Thereafter, a floating gate is formed over the inter-gate dielectric layer and the tunnel layer. Thereafter, a source region and a drain region are formed in the substrate beside two sides of the floating gate under the tunnel layer. Especially, the manufacturing method of the memory cell can be integrated with the manufacturing process of high operation voltage component and low operation voltage component.
1. An electrically erasable programmable read-only memory (EEPROM) cell, comprising:
an inter-gate dielectric layer and a tunnel layer, disposed over a surface of a substrate respectively;
a first well region and a second well region, with difference conductive type each other, disposed in the substrate;
a doped region, disposed in the substrate under the inter-gate dielectric layer and is used as a control gate;
a floating gate, disposed over the tunnel layer and the inter-gate dielectric layer,
a source region and a drain region, disposed in the first well region of two sides of the floating gate under the tunnel layer; and
wherein the tunnel layer is disposed on a surface of the first well region, and the inter-gate dielectric layer is disposed on a surface of the second well region, and the doped region used as the control gate is disposed in the second well region.
2. The EEPROM cell of claim 1 , wherein a thickness of the inter-gate dielectric layer is greater than a thickness of the tunnel layer.
3. The EEPROM cell of claim 1 , wherein a thickness of the inter-gate dielectric layer is in a range of about 30 nm to about 50 nm.
4. The EEPROM cell of claim 1 , further comprises:
a deeply doped region, disposed in the substrate under the tunnel layer, wherein the source region is disposed in the deeply doped region.