High performance data rate system for flash devices
View Patent ↗A Flash memory system includes N flash devices, where N is an integer, each flash device having a flash device interface consisting of a control signal line, a R/B signal line, and a I/O signal line, and wherein each flash device has an operating speed of s. A logic block is connected to each flash device interface, and is further connected to a controller which whose interfaces also has a control signal line, a R/B signal line, and a I/O signal line, so that controller operates at an operating speed of N times s, and wherein the logic block controls each flash device simultaneously.
1. A method for communicating between an IO bus and flash memory banks DEVICE A and DEVICE B, wherein the IO bus comprises signals SYS WE (Write Enable) and SYS DATA (SYSTEM DATA), both signals being data bit streams having a period pl, the method comprising the steps of:
1) generating a WE A (WRITE ENABLE to DEVICE A) signal WE having a period pl;
2) generating a WE B (WRITE ENABLE to DEVICE B) signal having a period pl;
3) generating a DATA A (DATA TO DEVICE A) signal whose valid start time is triggered by a rising edge of SYS WE, and whose value is that of the SYS DATA signal at the time of the rising edge of SYS WE, and maintained at that value for a period 2pl;
4) writing the DATA A into DEVICE A, triggered by the WE A signal;
5) generating a DATA B signal whose valid start time is triggered by the falling edge of SYS WE, and whose value is that of the SYS DATA signal at the time of the falling edge of SYS WE, and maintained at that value for a period 2pl;
6) writing the DATA B into DEVICE B, triggered by the WE B signal; and
7) repeating steps 3) through 6 for each successive rising edge of SYS WE, so that the bits of the data bit stream of SYS DATA are alternately written into DEVICE A and then into DEVICE B, each such writing done with a period of twice that of SYS DATA, and therefore at a frequency of one-half that of SYS DATA.
2. A method for communicating between an IO bus and flash memory banks DEVICE A and DEVICE B, wherein the IO bus comprises signals SYS RE (Read Enable) and SYS DATA (SYSTEM DATA), both signals being data bit streams having a period pl, the method comprising the steps of:
1) generating a RE A (READ ENABLE to DEVICE A) signal having a period pl;
2) generating a RE B (READ ENABLE to DEVICE B) signal having a period pl;
3) reading a DATA A signal, having a period of 2pl, from DEVICE A and writing it onto the SYS DATA signal, said reading triggered by the RE A signal, and said reading continuing for a period pl,
4) reading the DATA B signal, having a period of 2pl, from DEVICE B and writing it onto the SYS DATA signal, said reading triggered by the RE B signal, and said reading continuing for a period pl; and
5) repeating steps 3) and 4) for each successive rising edge of SYS WE,
so that the bits of the data bits of DEVICE A and DEVICE B are alternately read onto SYS DATA, each such writing done with a period one half of that of the DEVICE A or the DEVICE B signals, and therefore at a frequency of twice that of the DEVICE A or DEVICE B signals.
3. A method for communicating between an IO bus and flash memory banks DEVICE A and DEVICE B, wherein the IO bus comprises signals SYS WE (Write Enable), SYS RE (Read Enable), and SYS DATA (SYSTEM DATA), all three signals being data bit streams having a period pl, the method comprising the steps of:
1) generating a WE A (WRITE ENABLE to DEVICE A) signal WE having a period pl;
2) generating a WE B (WRITE ENABLE to DEVICE B) signal having a period pl;
3) generating a DATA A (DATA TO DEVICE A) signal whose valid start time is triggered by a rising edge of SYS WE, and whose value is that of the SYS DATA signal at the time of the rising edge of SYS WE, and maintained at that value for a period 2pl;
4) writing the DATA A into DEVICE A, triggered by the WE A signal;
5) generating a DATA B signal whose valid start time is triggered by the falling edge of SYS WE, and whose value is that of the SYS DATA signal at the time of the falling edge of SYS WE, and maintained at that value for a period 2pl;
6) writing the DATA B into DEVICE B, triggered by the WE B signal;
7) repeating steps 3) through 6) for each successive rising edge of SYS WE;
8) generating a RE A (READ ENABLE to DEVICE A) signal having a period pl;
9) generating a RE B (READ ENABLE to DEVICE B) signal having a period pl;
10) reading a DATA A signal, having a period of 2pl, from DEVICE A and writing it onto the SYS DATA signal, said reading triggered by the RE A signal, and said reading continuing for a period pl,
11) reading the DATA B signal, having a period of 2pl, from DEVICE B and writing it onto the SYS DATA signal, said reading triggered by the RE B signal, and said reading continuing for a period pl; and
12) repeating steps 10) and 11) for each successive rising edge of SYS WE,
so that the bits of the data bit stream of SYS DATA are alternately written into DEVICE A and then into DEVICE B, each such writing done with a period of twice that of SYS DATA, and therefore at a frequency of one-half that of SYS DATA, and
so that the bits of the data bits of DEVICE A and DEVICE B are alternately read onto SYS DATA, each such writing done with a period one half of that of the DEVICE A or the DEVICE B signals, and therefore at a frequency of twice that of the DEVICE A or DEVICE B signals.
4. The method of claim 3 , further comprising triggering the RE A, RE B, WE A, and WE B from the SYS WE signal.