Capacitor device of a semiconductor
View Patent ↗Embodiments relate to a capacitor having a high capacitance, a semiconductor device having the same, and a method for manufacturing the semiconductor device. In embodiments, the capacitor may include a lower electrode having a predetermined pattern, a dielectric layer formed on the lower electrode, and an upper electrode formed on the dielectric layer.
1. A device comprising:
a lower electrode having a prescribed pattern, wherein the lower electrode comprises a contact auxiliary layer, a lower metal layer, an etch stop layer, and an upper metal layer wherein the contact auxiliary layer comprises a double layer of titanium/titanium nitride;
a dielectric layer formed over the lower electrode; and
an upper electrode formed over the dielectric layer.
2. The device of claim 1 , wherein the dielectric layer and the upper electrode are formed over the pattern.
3. The device of claim 1 , wherein the upper electrode and the lower electrode are configured to face each other along a side and a lower surface of the pattern.
4. The device of claim 1 , wherein the lower metal layer and the upper metal layer comprise aluminum.
5. The device of claim 1 , wherein the etch stop layer comprises titanium.
6. The device of claim 1 , wherein the pattern penetrates the upper metal layer to expose the etch stop layer.
7. The device of claim 1 , wherein the pattern penetrates the upper metal layer and the etch stop layer to expose the lower metal layer.
8. The device of claim 1 , wherein the pattern comprises a plurality of patterns.
9. The device of claim 1 , wherein a width of the pattern ranges from 0.08 μm to 1 μm.
10. The device of claim 1 , wherein the upper electrode comprises a titanium layer and a titanium nitride layer.
11. A device comprising:
a first insulating layer formed over a semiconductor substrate;
a capacitor formed over the first insulating layer;
a metal interconnection formed in a same plane as that of the capacitor and configured to be spaced apart from the capacitor by a prescribed distance; and
a second insulating layer formed between the capacitor and the metal interconnection,
wherein the capacitor comprises a lower electrode, a dielectric layer, and an upper electrode, and a prescribed pattern is formed at the lower electrode and the lower electrode comprises a contact auxiliary layer, a lower metal layer, an etch stop layer, and an upper metal layer wherein the contact auxiliary layer comprises a double layer of titanium/titanium nitride.
12. The device of claim 11 , wherein the dielectric layer and the upper electrode are formed at the pattern.
13. The device of claim 11 , wherein the upper electrode and the lower electrode are configured to face each other along a side and a lower surface of the pattern.
14. The device of claim 11 , wherein the lower metal layer and the upper metal layer comprise aluminum.
15. The device of claim 11 , wherein the etch stop layer comprises titanium.
16. The device of claim 11 , wherein the pattern penetrates the upper metal layer to expose the etch stop layer.
17. The device of claim 11 , wherein the pattern penetrates the upper metal layer and the etch stop layer to expose the lower metal layer.
18. The device of claim 11 , wherein the pattern comprises a plurality of patterns.
19. The device of claim 11 , wherein a width of the pattern ranges from 0.08 μm to 1 μm.
20. The device of claim 11 , wherein the upper electrode comprises a titanium layer and a titanium nitride layer.