Method for fabricating strained-silicon CMOS transistors
View Patent ↗A semiconductor substrate having a first active region and a second active region for fabricating a first transistor and a second transistor is provided. A first gate structure and a second gate structure are formed on the first active region and the second active region and a first spacer is formed surrounding the first gate structure and the second gate structure. A source/drain region for the first transistor and the second transistor is formed. The first spacer is removed from the first gate structure and the second gate structure and a cap layer is disposed on the first transistor and the second transistor and the cap layer covering the second transistor is removed thereafter. An etching process is performed to form a recess in the substrate surrounding the second gate structure. An epitaxial layer is formed in the recess and the cap layer is removed from the first transistor.
1. A method for fabricating a strained-silicon CMOS transistor, comprising:
providing a semiconductor substrate having a first active region for fabricating a first transistor, a second active region for fabricating a second transistor, and an isolation structure disposed between the first active region and the second active region;
forming a first gate structure on the first active region and a second gate structure on the second active region;
forming a first spacer around the first gate structure and the second gate structure;
forming a source/drain region for the first transistor and a source/drain region for the second transistor;
removing the first spacer from the first gate structure and the second gate structure;
depositing a cap layer on the first transistor and the second transistor;
removing the cap layer disposed on the second transistor;
performing an etching process for forming a recess on the second gate structure and in the semiconductor substrate surrounding the second gate structure;
performing a selective epitaxial growth process for forming an epitaxial layer in the recess; and
removing the cap layer from the surface of the first transistor.
2. The method for fabricating a strained-silicon CMOS transistor of claim 1 , wherein the first gate structure comprises:
a first gate dielectric; and
a first gate, disposed on the first gate dielectric.
3. The method for fabricating a strained-silicon CMOS transistor of claim 1 , wherein the second gate structure comprises:
a second gate dielectric; and
a second gate, disposed on the second gate dielectric.
4. The method for fabricating a strained-silicon CMOS transistor of claim 1 , wherein the first transistor comprises an NMOS transistor and the second transistor comprises a PMOS transistor.
5. The method for fabricating a strained-silicon CMOS transistor of claim 1 , wherein the cap layer is a silicon oxide cap layer.
6. The method for fabricating a strained-silicon CMOS transistor of claim 1 , wherein the cap layer is a stress layer.
7. The method for fabricating a strained-silicon CMOS transistor of claim 6 , wherein the stress layer is a silicon nitride stress layer.
8. The method for fabricating a strained-silicon CMOS transistor of claim 6 , wherein the stress layer is a high tensile stress film.
9. The method for fabricating a strained-silicon CMOS transistor of claim 1 further comprising:
forming a second spacer around the first gate structure and the second gate structure after removing the cap layer from the surface of the first transistor;
disposing a metal layer on the first transistor and the second transistor;
performing a rapid thermal annealing process for forming a salicide layer on the first transistor and the second transistor; and
removing the un-reacted metal layer.
10. The method for fabricating a strained-silicon CMOS transistor of claim 9 further comprising forming a contact etch stop layer on the first transistor and the second transistor after forming the salicide layer.
11. The method for fabricating a strained-silicon CMOS transistor of claim 1 , wherein the epitaxial layer comprises silicon germanium.
12. A method for fabricating a strained-silicon CMOS transistor, comprising:
providing a semiconductor substrate having a first active region for fabricating a first transistor, a second active region for fabricating a second transistor, and an isolation structure disposed between the first active region and the second active region;
forming a first gate structure on the first active region and a second gate structure on the second active region;
forming a spacer around the first gate structure and the second gate structure;
forming a source/drain region for the first transistor and a source/drain region for the second transistor;
depositing a buffer layer and a stress layer on the first transistor and the second transistor;
removing the buffer layer and the stress layer from the second transistor;
performing an etching process for forming a recess on the second gate structure and in the semiconductor substrate surrounding the second gate structure;
performing a selective epitaxial growth process for forming an epitaxial layer in the recess; and
removing the buffer layer and the stress layer from the surface of the first transistor.
13. The method for fabricating a strained-silicon CMOS transistor of claim 12 , wherein the first gate structure comprises:
a first gate dielectric; and
a first gate, disposed on the first gate dielectric.
14. The method for fabricating a strained-silicon CMOS transistor of claim 12 , wherein the second gate structure comprises:
a second gate dielectric; and
a second gate, disposed on the second gate dielectric.
15. The method for fabricating a strained-silicon CMOS transistor of claim 12 , wherein the first transistor comprises an NMOS transistor and the second transistor comprises a PMOS transistor.
16. The method for fabricating a strained-silicon CMOS transistor of claim 12 , wherein the buffer layer is a silicon oxide buffer layer.
17. The method for fabricating a strained-silicon CMOS transistor of claim 12 , wherein the stress layer is a silicon nitride stress layer.
18. The method for fabricating a strained-silicon CMOS transistor of claim 12 , wherein the stress layer is a high tensile stress film.
19. The method for fabricating a strained-silicon CMOS transistor of claim 12 further comprising:
disposing a metal layer on the first transistor and the second transistor;
performing a rapid thermal annealing process for forming a salicide layer on the first transistor and the second transistor; and
removing the un-reacted metal layer.
20. The method for fabricating a strained-silicon CMOS transistor of claim 19 further comprising forming a contact etch stop layer on the first transistor and the second transistor after forming the salicide layer.
21. The method for fabricating a strained-silicon CMOS transistor of claim 12 , wherein the epitaxial layer comprises silicon germanium.