EEPROM array with well contacts
A semiconductor integrated circuit device includes a cell well, a memory cell array formed on the cell well and having a memory cell area and cell well contact area, first wiring bodies arranged in the memory cell area, and second wiring bodies arranged in the cell well contact area. The layout pattern of the second wiring bodies is the same as the layout pattern of the first wiring bodies. The cell well contact area comprises cell well contacts that have the same dopant type as the cell well and that function as source/drain regions of dummy transistors formed in the cell well contact area.
1. A semiconductor integrated circuit device comprising:
a cell well,
a memory cell array formed on the cell well and having a memory cell area and cell well contact area,
first wiring bodies arranged in the memory cell area, and
second wiring bodies arranged in the cell well contact area,
wherein a layout pattern of the first wiring bodies is the same as a layout pattern of the second wiring bodies,
wherein the first wiring bodies include bit lines, word lines and block selection lines, the second wiring bodies include cell well bias lines, word lines and block selection lines, the bit lines and cell well bias lines are formed by use of the same conductive layer and width of the bit line in a row direction is the same as width of the cell well bias line in the row direction,
wherein transistors each having a source/drain portion of the same conductivity type as the conductivity type of the cell well are formed below the cell well bias line and the cell well bias line is connected to the cell well via the source/drain portion of the above same conductivity type.
2. The device according to claim 1 , wherein transistors each having a source/drain portion of a conductivity type opposite to the conductivity type of the cell well are formed below the bit line, the bit line is connected to the transistors via the source/drain portions of the opposite conductivity type and connection portions between the cell well bias lines and the cell well and connection portions between the bit line and the transistors are aligned in the row direction.
3. The device according to claim 2 , wherein charge storage layers which are insulated from the word lines are provided below the word lines, and conductive layers which are formed by use of the same conductive body as the charge storage layer and formed in electrical contact with the block selection lines are provided below the block selection lines.
4. The device according to claim 1 , wherein charge storage layers which are insulated from the word lines are provided below the word lines, and conductive layers which are formed by use of the same conductive body as the charge storage layer and formed in electrical contact with the block selection lines are provided below the block selection lines.