IP Library Granted Patent US 7,659,169
Granted Patent B2
US 7,659,169 · App. 11/574,341 · Granted Feb 9, 2010

Semiconductor device and method of manufacturing thereof

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Quick Facts
Patent No.
US 7,659,169
App. No.
11/574,341
Granted
Feb 9, 2010
Kind
B2
Abstract

There is a method of manufacturing a semiconductor device with a dual gate field effect transistor, the method including a semiconductor body a semiconductor material having a surface with a source region and a drain region of a first conductivity type and with a channel region of a second conductivity type opposite to the first conductivity type between the source region and the drain region and with a first gate region separated from the surface of the semiconductor body by a first gate dielectric above the channel region and with a second gate region situated opposite to the first gate region and formed within a recess in an opposite surface of the semiconductor body so as to be separated from the channel region by a second gate dielectric wherein the recess is formed with a local change of the doping of the channel region and by etching starting from the opposite surface of the semiconductor body.

Claims (13)

1. Method of manufacturing a semiconductor device with a dual gate field effect transistor, in which method

a semiconductor body of a semiconductor material is provided at a surface thereof with a source region and a drain region of a first conductivity type and

with a channel region of a second conductivity type opposite to the first conductivity type between the source region and the drain region and

with a first gate region separated from the surface of the semiconductor body by a first gate dielectric above the channel region and with a second gate region situated opposite to the first gate region and formed within a recess in an opposite surface of the semiconductor body so as to be separated from the channel region by a second gate dielectric,

wherein the recess is formed by means of a local change of the doping of the channel region and by performing an etching step starting from the opposite surface of the semiconductor body, characterized in that the local change of the doping of the channel region is provided close to the surface of the semiconductor body and in that the semiconductor body in the channel region is etched with an etching agent for the material of the semiconductor body and the local change of the doping of the channel region is used as an etch stop region.

2. Method according to claim 1 , characterized in that for the local change in the doping of the channel region a retrograde doping concentration profile in the channel region is used.

3. Method according to claim 2 , characterized in that the retrograde doping concentration of the channel region is obtained by implanting impurities of the second conductivity type from the surface of the semiconductor body.

4. Method according to claim 1 , characterized in that for the local change in the doping of the channel region a change in the conductivity type in the channel region is used.

5. Method according to claim 1 , characterized in that the source and drain regions are formed before the recess is formed and are used as further etch stop regions when the walls of the recess are being formed.

6. Method according to claim 1 , characterized in that after reaching the etch stop region, said etch stop region is removed by further etching.

7. Method according to claim 1 , characterized in that after the formation of the recess, the bottom and the walls thereof are provided with a dielectric layer and the recess is filled with the material of the second gate region.

8. Method according to claim 1 , characterized in that an electrochemical etching technique is used to form the recess.

9. Method according to claim 1 , characterized in that a silicon-on-insulator wafer is used for forming the dual gate transistor and the second gate region is formed using a substrate transfer technique with a further wafer.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 3, 2012
From: NXP B.V.
To: IMEC
Reel/Frame 027654/0244 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 8, 2007
From: SURDEANU, RADU; HIJZEN, ERWIN; ZANDT, MICHAEL ANTOINE; HUETING, RAYMOND JOSEPHUS
To: NXP B.V.
Reel/Frame 019928/0697 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2007
From: KONINKLIJKE PHILIPS ELECTRONICS N.V.
To: NXP B.V.
Reel/Frame 019719/0843 →