Semiconductor devices including voltage-sustaining space-charge zone and methods of manufacture thereof
View Patent ↗There is a method of manufacturing a semi conductor device that comprises source and drain regions of a first conductivity type, and a channel-accommodating region of a second, opposite conductivity type which separates the source and drain regions. The device comprises a gate which extends adjacent to the channel-accommodating region. The method includes the steps of etching a trench into the semiconductor body of the device at a location laterally spaced from that of the gate; and implanting a second conductivity type dopant into the body through the bottom of the trench to form a second conductivity type localised region in the drain region. The dimensions and doping level of the localised level of the localised region in the finished device is such that the localised region and adjacent portions of the drain region provide a voltage-sustaining space-charge zone when depleted.
1. A method of manufacturing a semiconductor device including a semiconductor body, the semiconductor body comprising top and bottom major surfaces, source and drain regions of a first conductivity type, and a channel-accommodating region of a second, opposite conductivity type which separates the source and drain regions, the device further comprising a gate which extends adjacent to the channel-accommodating region, including the steps of:
(a) etching a trench into the top major surface of the body at a location laterally spaced from that of the gate; and
(b) implanting a second conductivity type dopant into the body through the bottom of the trench to form a second conductivity type localised region in the drain region, the dimensions and doping level of the localised region in the finished device being such that the localised region and adjacent portions of the drain region provide a voltage-sustaining space-charge zone when depleted.
2. The method of claim 1 wherein the drain region comprises a drain contact region and a drain drift region, with the drain drift region between the channel-accommodating region and the drain contact region, and the drain drift region is doped to a lesser extent than the drain contact region, wherein the localised region extends substantially across the drain drift region towards the drain contact region.
3. The method of claim 2 wherein the gate is either a trench gate or planar gate.
4. The method of claim 1 wherein the localised region in the finished device is elongated in a direction perpendicular to the top major surface of the semiconductor body.
5. The method of claim 4 wherein the gate is either a trench gate or planar gate.
6. The method of claim 1 wherein step (b) comprises a plurality of implantations of the second conductivity type dopant at different energies.
7. The method of claim 6 wherein the gate is either a trench gate or planar gate.
8. The method of claim 6 , wherein the plurality of implantations are performed at four different energies.
9. The method of claim 1 wherein the doping profile of the localised region in the finished device in a direction perpendicular to the top major surface of the semiconductor body is substantially uniform.
10. The method of claim 9 wherein the gate is either a trench gate or planar gate.
11. The method of claim 1 further including the steps of:
(c) depositing a layer of insulating material over the sidewalls and bottom of the trench; and
(d) depositing material in the trench over the insulating layer to provide an electrode therein.
12. The method of claim 11 further including the steps of:
(e) providing a source electrode in contact with the source region; and
(f) providing a connection between the electrode deposited in the trench and the source electrode of the device.
13. The method of claim 12 wherein the gate is either a trench gate or planar gate.
14. The method of claim 11 wherein the gate is either a trench gate or planar gate.
15. The method of claim 1 wherein the gate is a trench-gate.
16. The method of claim 1 wherein the gate is a planar gate.
17. A semiconductor device manufactured by the method of claim 1 .