Hard macro with configurable side input/output terminals, for a subsystem
A hard macro device (HMD), for a subsystem (TMi) such as a data processor, comprises a processing core (C) provided with at least one time critical input terminal (CIT) adapted to feed it with time critical input data to be processed and at least one time critical output terminal (COT) adapted to deliver time critical output data it has processed. The processing core (C) is surrounded at least partly by a connecting interface zone (CIZ) comprising i) at least one input group of at least two time critical auxiliary input terminals (AITj), located at chosen locations and adapted to receive time critical input data to be processed, and/or at least one output group of at least two time critical auxiliary output terminals (AOTk), located at chosen locations and adapted to deliver processed time critical output data, ii) an input connecting means (LO) for connecting each time critical auxiliary input terminal (AITj) of this input group to the time critical input terminal (CIT), and/or iii) an output connecting means (Bk) for connecting the time critical output terminal (COT) to each time critical auxiliary output terminal (AOTk) of this output group.
1. Hard macro device (HMD) for a subsystem (TMi), said hard macro device (HMD) comprising
a processing core (C) provided with at least one time critical input terminal (CIT) adapted to feed it with time critical input data to be processed and at least one time critical output terminal (COT) adapted to deliver time critical output data it has processed, wherein processing core (C) is surrounded at least partly with a connecting interface zone (CIZ) with an external border having one or more sides, the (CIZ) including,
i) at least one input group of at least two time critical auxiliary input terminals (AITj), located at predetermined sides on the external border of the (CIZ) and adapted to receive time critical input data to be processed, and at least one output group of at least two time critical auxiliary output terminals (AOTk), located at predetermined sides on the external border of the (CIZ) and adapted to deliver processed time critical output data, the critical auxiliary input terminals (AITj) and critical auxiliary output terminals (AOTk) located at the border of the HMD,
ii) an input connecting means (LO) for connecting each time critical auxiliary input terminal (AITj) of said input group to said time critical input terminal (CIT), and
iii) an output connecting means (Bk) for connecting said time critical output terminal (COT) to each time critical auxiliary output terminal (AOTk) of said output group.
2. Hard macro device according to claim 1 , characterized in that said input connecting means comprises at least one integrated component (LO) defining a logical OR gate connected to said time critical input terminal (CIT) and to as many input conductive tracks as time critical auxiliary input terminals (AITj) in said input group, each input conductive track being connected to one of said time critical auxiliary input terminals (AITj).
3. Hard macro device according to claim 1 , characterized in that said output connecting means (Bk) comprises as many output conductive tracks as time critical auxiliary output terminals (AOTk) in said output group, each output conductive track connecting one of said time critical auxiliary output terminals (AOTk) to said time critical output terminal (COT).
4. Hard macro device according to claim 3 , characterized in that each of said output conductive tracks comprises a buffer component (Bk) for buffering processed time critical output data to be delivered.
5. Hard macro device according to claim 1 , characterized in that said connecting interface zone (CIZ) at least partly surrounds said processing core (C) , and in that said time critical auxiliary input terminals (AITj) of said input group are located on at least two sides of said connecting interface zone (CIZ), and said time critical auxiliary output terminals (AOTk) of said output group are located on said two sides of said connecting interface zone (CIZ).
6. Hard macro device according to claim 5 , characterized in that said connecting interface zone (CIZ) comprises four sides perpendicular to one another and fully surrounding said core (C), and it also comprises an input group having a maximum of four time critical auxiliary input terminals (AITj) each located on one of its sides.
7. Hard macro device according to claim 5 , characterized in that said connecting interface zone (CIZ) comprises four sides perpendicular to one another and fully surrounding said core (C), and it also comprises an output group of at least four time critical auxiliary output terminals (AOTk) each located on one of its sides.
8. Hard macro device-according to claim 1 , characterized in that said processing core (C) comprises
at least one non-time critical input terminal (CIT′) adapted to feed it with non-time critical input data to be processed and at least one non-time critical output terminal (COT′) adapted to deliver non-time critical output data processed by said core (C), and in that said connecting interface zone (CIZ) comprises
i) as many non-time critical auxiliary input terminals (AIT′) as non-time critical input terminals (CIT′) and as many auxiliary input conductive tracks as non-time critical input terminals (CIT′), each of said auxiliary input conductive tracks connecting one of said non-time critical auxiliary input terminals (AIT′) to a corresponding one of said non-time critical input terminals (CIT′), and
ii) as many non-time critical auxiliary output terminals (AOT′) as non-time critical output terminals (COT′) and as many auxiliary output conductive tracks as non-time critical output terminals (COT′), each of said auxiliary output conductive tracks connecting one of said non-time critical auxiliary output terminals (AOT′) to a corresponding one of said non-time critical output terminals (COT′).
9. Hard macro device according to claim 1 , characterized in that it constitutes an integrated circuit.
10. Subsystem (TMi) characterized in that it comprises at least one hard macro device (HMD) according to claim 1 .
11. Subsystem according to claim 10 , characterized in that it constitutes a data processor.
12. Subsystem according to claim 11 , characterized in that said data processor is a microprocessor.