Dual bias control circuit
The present invention relates to a bias control circuit and method for supplying a bias signal to at least one stage of an amplifier circuit, wherein a dual bias control is provided by generating a bias current and additionally using this bias current to derive a control signal for limiting a supply voltage of the at least one amplifier stage in response to the control signal. Thereby, a compression of the output signal of the amplifier stage, which results from the voltage limitation, can be realized in addition to the base current steering. This leads to a decrease in small signal gain and thus reduced output noise.
1. In a circuit arrangement having cascaded amplification stages, each of which feeds into the next, and each drawing operating power from a power terminal that provides a supply voltage, a circuit comprising:
at least a first one of the cascade amplification stages configured and arranged to provide an rf output signal to the next amplification stage,
a control circuit configured to generate
a bias control signal that provides a bias current used to set a bias point at which to operate the first one of the amplification stages;
a voltage limitation control signal derived from the bias current; and
a voltage limitation circuit, configured and arranged for receiving the voltage limitation control signal and coupled between the power terminal and an input port of the amplification stage, the input port configured and arranged to provide a voltage-limited voltage to at least said first one of the amplification stages, to provide the rf output signal to the next amplification stage.
2. A circuit according to claim 1 , wherein said control circuit includes a voltage-to-current converter having a predetermined current control characteristic.
3. A circuit according to claim 2 , wherein said control circuit includes a current mirror circuit for copying an output current of said voltage-to-current converter to generate said bias current and a second current, wherein said second current is supplied to a voltage buffer circuit for generating said voltage limitation control signal.
4. A circuit according to claim 3 , wherein said voltage buffer circuit comprises an operational amplifier connected to a resistor through which said second current is caused to flow.
5. A bias control circuit according to claim 1 , wherein said voltage limitation circuit comprises a variable resistor connected between the power terminal and said at least one amplification stage.
6. A circuit according to claim 5 , wherein said variable resistor comprises a transistor which is arranged to receive said voltage limitation control signal at a control terminal thereof.
7. A circuit according to claim 1 , further including at least two of said control circuits and voltage limitation circuits allocated to a respective stage of said amplifier circuit.
8. An amplifier circuit comprising:
a power terminal that provides a supply voltage;
a plurality of amplification stages each drawing operating power from the power terminal, and each biased by separately-driven current-bias signals;
a control circuit configured to generate
a bias control signal that provides a bias current used to provide one of the current bias signals and to set a bias point at which to operate a first one of the amplification stages, and
a voltage limitation control signal derived from the bias current; and
a voltage limitation circuit coupled between the power terminal and an input port of the amplification stage, the input port configured and arranged to provide a voltage-limited voltage to each of the amplification stages.
9. The amplifier circuit of claim 8 , wherein said control circuit includes a voltage-to-current converter having a predetermined current control characteristic.
10. The amplifier circuit of claim 9 , wherein said control circuit includes a current mirror circuit for copying an output current of said voltage-to-current converter to generate said bias current and a second current, wherein said second current is supplied to a voltage buffer circuit for generating said voltage limitation control signal.
11. The amplifier circuit of claim 10 , wherein said voltage buffer circuit_comprises an operational amplifier connected to a resistor through which said second current is caused to flow.
12. The amplifier circuit of claim 8 , wherein said voltage limitation circuit comprises a variable resistor connected between the power terminal and said at least one amplification stage.
13. The amplifier circuit of claim 12 , wherein said variable resistor comprises a transistor which is arranged to receive said voltage limitation control signal at a control terminal thereof.
14. The amplifier circuit of claim 8 , wherein said control circuit includes a voltage-to-current converter having a predetermined current control characteristic, and wherein said voltage limitation circuit comprises a variable resistor connected between the power terminal and said at least one amplification stage.
15. In a circuit arrangement having multiple amplification stages, each drawing operating power from a power terminal that provides a supply voltage, a circuit comprising:
a control circuit including a voltage-to-current converter having a predetermined current control characteristic and being configured to generate a bias current and a second current, wherein the bias control signal provides a bias current used to set a bias point at which to operate a first one of the amplification stages and the second current is supplied to a voltage buffer circuit for generating said voltage limitation control signal;
a voltage limitation control signal at least predominantly based on the bias current; and
a voltage limitation circuit, configured and arranged for receiving the voltage limitation control signal and coupled between the power terminal and an input port of the amplification stage, the input port configured and arranged to provide a voltage-limited supply voltage to at least one of the amplification stages.