Semiconductors device and method of manufacturing such a device
View Patent ↗The invention relates to a semiconductor device ( 10 ) comprising a semiconductor body ( 1 ) with a high-ohmic semi-conductor substrate ( 2 ) which is covered with a dielectric layer ( 3, 4 ) containing charges, on which dielectric layer one or more passive electronic components ( 20 ) comprising conductor tracks ( 20 ) are provided, wherein, at the location of the passive elements ( 20 ), a region ( 5 ) is present at the interface between the semiconductor substrate ( 2 ) and the dielectric layer ( 3, 4 ), as a result of which the conductivity of an electrically conducting channel induced in the device ( 10 ) by the charges is limited at the location of the region ( 5 ). According to the invention, the region ( 5 ) is formed by deposition and comprises a semi-insulating material. As a result, the device ( 10 ) has a very low high-frequency power loss because the inversion channel is formed in the semi-insulating region ( 5 ). The device ( 10 ) further allows for a higher temperature budget and hence for the integration of active semiconductor elements ( 8 ) into the semiconductor body ( 1 ). A very suitable semi-insulating material for the region ( 5 ) is SiC, SIPOS or POLYDOX.
1. A semiconductor device comprising a high-ohmic semiconductor substrate which is covered with a dielectric layer which contains charges, on which dielectric layer one or more passive electronic elements including conductor tracks are situated, wherein, at the location of the passive elements a region is situated at the interface between the semiconductor substrate and the dielectric layers, causing the electrical conductivity of an electroconductive channel induced in the semiconductor device by the charges to be decreased at the location of the region characterized in that the region is formed by deposition and comprises a semi-insulating material.
2. A semiconductor device as claimed in claim 1 , characterized in that the semi-insulating material of the deposited region comprises a mixture of silicon and oxygen.
3. A semiconductor device as claimed in claim 1 , characterized in that the resistivity of the semi-insulating material ranges between 10 kΩcm and 30 GΩ.cm, and preferably between 1 MΩcm and 1 GΩ.cm.
4. A semiconductor device as claimed in claim 1 , characterized in that the semi-insulating material is a Sic compound.
5. A semiconductor device as claimed in claim 4 , characterized in that the stress in an as-deposited layer of the SiC compound material is below 360 MPa.
6. A semiconductor device as claimed in claim 1 , characterized in that the region is situated at the bottom of a recess formed in the semiconductor substrate.
7. A semiconductor device as claimed in claim 1 characterized in that the region comprises a number of mutually separated strip-shaped sub-regions.
8. A method of manufacturing a semiconductor device
wherein a dielectric layer comprising charges is formed on a high-ohmic semiconductor substrate and one or more passive electronic elements including conductor tracks are provided, on said dielectric layer, and
wherein, at the location of the passive elements a region is formed at the interface between the semiconductor substrate and the dielectric layer as a result of which the electrical conductivity of an electroconductive channel induced in the semiconductor device by the charges is reduced at the location of the region
characterized in that the region is formed by means of deposition, and a semi-insulating material is selected as the material for the region.
9. A method as claimed in claim 8 , characterized in that a mixture of silicon and oxygen is chosen as the semi-insulating material.
10. A method as claimed in claim 8 characterized in that the resistivity of the semi-insulating material is chosen in ranges between 10 kΩcm and 30 GΩcm, and preferably between 1 MΩcm and 1 GΩcm.
11. A method as claimed in claim 8 , characterized in that the semiinsulating layer is deposited prior to a manufacturing process of an active semiconductor element in the substrate.
12. A method as claimed in claim 8 , characterized in that the semiinsulating material of the layer comprises silicon and carbon.
13. A method as claimed in claim 12 , characterised in that the SiC layer is amorphous.
14. A method of manufacturing a semiconductor device
wherein a dielectric layer comprising charges is formed on a high-ohmic semiconductor substrate and one or more passive electronic elements including conductor tracks are provided, on said dielectric layer, and
wherein, at the location of the passive elements a region is formed at the interface between the semiconductor substrate and the dielectric layer as a result of which the electrical conductivity of an electroconductive channel induced in the semiconductor device by the charges is reduced at the location of the region
characterized in that the region is formed by means of deposition, and a semi-insulating material is selected as the material for the region, wherein the semiconductor substrate a recess is formed a side wall of which is covered with an insulating spacer after which a thin semi-insulating layer is deposited on the surface of the device as well as a dielectric layer by means of which the recess is filled completely, after which the device is planarized by chemical-mechanical polishing, in which process the parts of semi-insulating layer and dielectric layer that are situated outside the recess are removed.
15. A method as claimed in claim 14 , characterized in that the insulating spacer is formed by subjecting the walls and the bottom of the recess to a thermal oxidation treatment, after which the thermal oxide formed at the bottom of the recess is removed again by means of anisotropic etching.
16. A method as claimed in claim 14 , characterized in that a part of the semi-insulating layer bordering on the surface of the device is converted into a dielectric region by oxidation.