IP Library Granted Patent US 7,671,768
Granted Patent B2
US 7,671,768 · App. 11/579,016 · Granted Mar 2, 2010

Digital-to-analogue converter system with increased performance

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Quick Facts
Patent No.
US 7,671,768
App. No.
11/579,016
Granted
Mar 2, 2010
Kind
B2
Abstract

The invention relates to an N-bit digital-to-analogue converter (DAC) system, comprising—a DAC unit comprising an N-bit master DAC and a slave DAC, yielding a master DAC unit output signal and a slave DAC unit output signal, respectively, said N-bit master DAC having an output step size,—an adder unit combining the master DAC unit output signal and the slave DAC unit output signal, and—a means for storing correction values for at least the master DAC, said correction values being used by the slave DAC, whereby the DAC system is arranged for master DAC output corrections with a size in absolute value higher than half of the output step size.

Claims (21)

1. A N-bit digital-to-analogue converter (DAC) system, comprising

a DAC unit comprising an N-bit master DAC and a slave DAC, yielding a master DAC unit output signal and a slave DAC unit output signal, respectively, said N-bit master DAC having an output step size,

an adder unit combining said master DAC unit output signal and said slave DAC unit output signal, and

a means for storing correction values for at least said master DAC, said correction values being used by said slave DAC,

whereby said DAC system is arranged for master DAC output corrections with a size in absolute value higher than half of said output step size.

2. A N-bit digital-to-analogue converter (DAC) system as in claim 1 , wherein said master DAC output corrections are performed directly or indirectly.

3. A N-bit DAC system as in claim 1 , further comprising a processing unit, said processing unit generating an input signal to said slave DAC.

4. A N-bit DAC system as in claim 1 , wherein said slave DAC has a resolution of N bits or less.

5. A N-bit DAC system as in claim 1 , wherein said master DAC unit output signal and said slave DAC unit output signal are current outputs.

6. A N-bit DAC system as in claim 1 , wherein said master DAC unit output signal and said slave DAC unit output signal are voltage outputs.

7. A N-bit DAC system as in claim 6 , further comprising current-to-voltage converters for obtaining said voltage outputs.

8. A N-bit DAC system as in claim 7 , wherein said slave DAC unit output signal is applied to a voltage divider.

9. A N-bit DAC system as in claim 1 , whereby said means for storing correction values is arranged for storing less than 2 N correction values.

10. A N-bit DAC system as in claim 1 , mounted on a Printed Circuit Board.

11. A N-bit DAC system as in claim 1 , said DAC system being integrated monolithically.

12. A N-bit DAC system as in claim 1 , wherein said means for storing is an EPROM, placed on a printed circuit board or integrated monolithically.

13. A method for determining said correction values of an N-bit DAC system as in claim 1 , comprising the steps of:

determining the performance of said N-bit master DAC, and

calculating based on said determined performance said correction values, characterised in that said step of performance determining is carried out via either DC measurements or AC measurements.

14. A method for determining said correction values as in claim 13 , wherein said DC measurements comprise performing DC voltage measurements for a selected subset of all possible input codes, said subset being selected such that any other input code can be constructed with said selected input codes, and wherein said step of calculating correction values comprises calculating correction codes for input codes, not belonging to said selected subset.

15. A method for determining said correction values as in claim 13 , wherein said AC measurements are carried out by applying a plurality of sine waves to said master DAC, determining distortion spectra from said DAC system's output signal, and calculating said correction values from said distortion spectra.

Assignments (2)
CHANGE OF NAME Recorded Dec 4, 2009
From: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC)
To: IMEC
Reel/Frame 023594/0846 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 22, 2008
From: DE CEUNINCK, WARD
To: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC); UNIVERSITEIT HASSELT
Reel/Frame 021722/0554 →