Structurally-enhanced integrated circuit package and method of manufacture
View Patent ↗A chip scale integrated circuit package includes an integrated circuit chip which has a first face and a second face. A plurality of pillar bumps are formed on the first face of the integrated circuit chip. An encapsulant material encapsulates the sides and the first face of the integrated circuit chip, and the pillar bumps. Upper ends of the pillar bumps remain free from encapsulant material and a substantially planar surface is formed by an upper surface of the encapsulant material and the upper ends of the pillar bumps. A plurality of solder balls are mounted on the substantially planar surface in locations corresponding to the upper ends of the pillar bumps.
1. A chip scale integrated circuit package, comprising:
an integrated circuit chip, having a first face and a second face;
a plurality of pillar bumps formed on the first face of the integrated circuit chip;
an encapsulant material encapsulating the sides and first face of the integrated circuit chip, and the pillar bumps, such that upper ends of the pillar bumps remain free from encapsulant material and such that a substantially planar surface is formed by an upper surface of the encapsulant material and the upper ends of the pillar bumps; and
a die pad having a footprint smaller than a footprint of the integrated circuit chip and having a first face and a second face;
wherein the encapsulant material further encapsulates the second face of the integrated circuit chip and the sides of the die pad.
2. The chip scale integrated circuit package according to claim 1 , further comprising:
an adhesive layer formed on the first face of the die pad;
wherein the second face of the integrated circuit chip is mounted on the first face of the die pad via the adhesive layer.
3. The chip scale integrated circuit package according to claim 1 , further comprising a plurality of solder balls mounted on the substantially planar surface in locations corresponding to the upper ends of the pillar bumps.
4. A chip scale integrated circuit package, comprising:
an integrated circuit chip, having a first face and a second face;
a plurality of pillar bumps formed on the first face of the integrated circuit chip;
an encapsulant material encapsulating the sides and first face of the integrated circuit chip, and the pillar bumps, such that upper ends of the pillar bumps remain free form encapsulant material and such that a first substantially planar surface is formed by an upper surface of the encapsulant material and the upper ends of the pillar bumps;
a second encapsulant material encapsulating the first substantially planar surface and the first plurality of solder balls such that an upper portion of each of the first plurality of solder balls remains free from the second encapsulant material; and
a die pad having a footprint smaller than a footprint of the integrated circuit chip and having a first face and a second face;
wherein the encapsulant material further encapsulates the second face of the integrated circuit chip and the sides of the die pad.
5. The chip scale integrated circuit package according to claim 4 , further comprising:
an adhesive layer formed on the first face of the die pad;
wherein the second face of the integrated circuit chip is mounted on the first face of the die pad via the adhesive layer.
6. The chip scale integrated circuit package according to claim 4 , further comprising:
a first plurality of solder balls mounted on the first substantially planar surface in locations corresponding to the upper ends of the pillar bumps; and
a second plurality of solder balls mounted on the upper portions of the first solder balls.
7. A method of assembling a chip scale integrated circuit package, comprising:
a) applying an adhesive to a plurality of die pad portions of a leadframe;
b) mounting an integrated circuit chip to each of the plurality of die pad portions via the adhesive, where the footprint of each of the integrated circuit chips is larger than the footprint of each of the plurality of die pad portions;
c) attaching the die pad portions to a carrier;
d) forming pillar bumps on the upper face of each of the integrated circuit chips;
e) applying a release film over the integrated circuit chips such that the release film is in contact with the upper ends of the pillar bumps, thereby forming a cavity in which the integrated circuit chips are located;
f) injecting encapsulant into the cavity;
g) curing the encapsulant;
h) removing the release film; and
i) affixing a plurality of solder balls to the upper ends of the pillar bumps.
8. The method according to claim 7 , further comprising:
j) applying a layer of second encapsulant material around the solder balls such that an upper portion of each of the solder balls remains free from the layer of second encapsulant material; and
k) affixing a second plurality of solder balls to the upper portions of each of the plurality of solder balls.
9. The method according to claim 8 , further comprising:
g) applying a layer of second encapsulant material around the solder balls such that an upper portion of each of the solder balls remains free from the layer of second encapsulant material; and
h) affixing a second plurality of solder balls to the upper portions of each of the plurality of solder balls.
10. A method of assembling a chip scale integrated circuit package, comprising:
a) attaching the lower face of a plurality of integrated circuit chips to a carrier;
b) applying a release film over the integrated circuit chips such that the release film is in contact with the upper ends of pillar bumps formed on the upper face of each of the integrated circuit chips, thereby forming a cavity in which the integrated circuit chips are located;
c) injecting encapsulant into the cavity;
d) curing the encapsulant;
e) removing the release film; and
f) affixing a plurality of solder balls to the upper ends of the pillar bumps.