Semiconductor memory device having input first-stage circuit
View Patent ↗A semiconductor memory device of the present invention determines a logic level of a signal based on a predetermined reference voltage. And the memory device has an input terminal to which a reference signal having the reference voltage is input, a low-pass filter connected to the input terminal for passing a component of the reference voltage of the reference signal and eliminating undesired high frequency components, and one or more input first-stage circuits to each of which an output of the low-pass filter and a signal having the logic level to be determined are connected. In the memory device, the low-pass filter has predetermined attenuation at least at a frequency of an operating clock.
1. A semiconductor device comprising, on a single semiconductor chip:
a plurality of DQ terminals each receiving a DQ signal supplied from outside of the semiconductor device;
a plurality of input circuits each including a first input node coupled to a corresponding one of the DQ terminals to receive the DQ signal and a second input node supplied with a reference voltage, and comparing the DQ signal with the reference voltage to produce an output signal at an output node thereof;
a second terminal receiving a DC voltage supplied from the outside of the semiconductor device; and
a low-pass filter coupled at one end thereof to the second terminal and at the other end thereof in common to the second input nodes of the input circuits, the low-pass filter transmitting the DC voltage from the second terminal to each of the second input nodes of the input circuits as the reference voltage and attenuating a noise signal which may be supplied to the second terminals together with the DC voltage from the outside of the semiconductor device so that a difference between the reference voltage and the DC voltage caused by the noise signal is suppressed.
2. The semiconductor device as claimed in claim 1 , wherein the device is supplied with a power supply voltage, the DC voltage takes a half voltage of the power supply voltage.
3. The semiconductor device as claimed in claim 1 , wherein an attenuation amount of the low-pass filter is greater than approximately 6 dB at a frequency of 100 MHz.
4. The semiconductor device as claimed in claim 1 , wherein the low-pass filter includes a plurality of capacitors, and each of the capacitors is arranged in a vicinity of a corresponding one of the second input nodes of the input circuits.
5. The device as claimed in claim 1 , further comprising a power supply node supplying the low-pass filter with a power supply voltage, and wherein the low-pass filter includes a transistor coupled between an output node thereof and the power supply node, a differential amplifier circuit including a second output node coupled to a control electrode of the transistor, and a mirror capacitor coupled between the second output node of the differential amplifier and the output node of the low-pass filter.
6. A memory module comprising:
a circuit board;
a wiring layer formed on the circuit board to convey a DC voltage; and
a plurality of semiconductor devices mounted on the circuit board, each of the semiconductor devices comprising, on a single semiconductor chip;
a plurality of DQ terminals each receiving a DQ signal supplied from outside of the single semiconductor device,
a plurality of input circuits each including a first input node coupled to a corresponding one of the DQ terminals to receive the DQ signal and a second input node supplied with a reference voltage, and comparing the DQ signal with the reference voltage to produce an output signal at an output node thereof,
a second terminal, and
a low-pass filter coupled at one end thereof to the second terminal and at the other end thereof in common to the second input nodes of the input circuits;
the second terminals of the semiconductor devices being connected in common to the wiring layer to receive the DC voltage,
each of the low-pass filters of the semiconductor devices transmitting the DC voltage from the second terminal of an associated one of the semiconductor devices to the second input nodes of the input circuits of the associated one of the semiconductor devices as the reference voltage and attenuating a noise signal which may be supplied to the second terminals together with the DC voltage from outside of the associated one of the semiconductor devices so that a difference between the reference voltage and the DC voltage caused by the noise signal is suppressed.
7. The memory module as claimed in claim 6 , wherein each of the semiconductor devices is supplied with a power supply voltage, and each of the DC voltage takes a half voltage of the power supply voltage supplied to an associated one of the semiconductor devices.
8. The memory module as claimed in claim 6 , wherein an attenuation amount of each of low-pass filters of the semiconductor devices is greater than approximately 6 dB at a frequency of 100 MHz.
9. The memory module as claimed in claim 6 , wherein each of plurality of the low-pass filters of the semiconductor devices includes a plurality of capacitors, and each of the capacitors is arranged in a vicinity of a corresponding one of the second input nodes of the input circuits of an associated one of the semiconductor device.
10. The memory module as claimed in claim 6 , wherein each of the semiconductor devices further comprises a power supply node supplying the low-pass filter thereof with a power supply voltage, each the of the of low-pass filters of the semiconductor devices includes a transistor coupled between an output node thereof and the power supply node of an associated one of the semiconductor devices, a differential amplifier circuit including a second output node coupled to a control electrode of the transistor, and a mirror capacitor coupled between the second output node of the differential amplifier and the output node thereof.
11. A system comprising:
a generator generating a DC voltage; and
a memory module comprising;
a circuit board;
a wiring layer formed on the circuit board to convey the DC voltage; and
a plurality of semiconductor devices mounted on the circuit board, each of the semiconductor devices comprising, on a single semiconductor chip;
a plurality of DQ terminals each receiving a DQ signal supplied from outside of the single semiconductor device,
a plurality of input circuits each including a first input node coupled to a corresponding one of the DQ terminals to receive the DQ signal and a second input node supplied with a reference voltage, and comparing the DQ signal with the reference voltage to produce an output signal at an output node thereof,
a second terminal, and
a low-pass filter coupled at one end thereof to the second terminal and at the other end thereof in common to the second input nodes of the input circuits;
the second terminals of the semiconductor devices being connected in common to the wiring layer to receive the DC voltage,
each of the low-pass filters of the semiconductor devices transmitting the DC voltage from the second terminal of an associated one of the semiconductor devices to the second input nodes of the input circuits of the associated one of the semiconductor devices as the reference voltage and attenuating a noise signal which may be supplied to the second terminals together with the DC voltage from outside of the associated one of the semiconductor devices so that a difference between the reference voltage and the DC voltage caused by the noise signal is suppressed.
12. The system as claimed in claim 11 , wherein each of the semiconductor devices is supplied with a power supply voltage, and each of the DC voltage takes a half voltage of the power supply voltage supplied to an associated one of the semiconductor devices.
13. The system as claimed in claim 11 , wherein an attenuation amount of each of the low-pass filters of the semiconductor devices is greater than approximately 6 dB at a frequency of 100 MHz.
14. The system as claimed in claim 11 , wherein each of the low-pass filters of the semiconductor devices includes a plurality of capacitors, and each of the capacitors is arranged in a vicinity of a corresponding one of the second input nodes of the input circuits of an associated one of the semiconductor device.
15. The system as claimed in claim 11 , wherein each of the semiconductor devices further comprises a power supply node supplying the low-pass filter thereof with a power supply voltage, each of the low-pass filters of the semiconductor devices includes a transistor coupled between an output node thereof and the power supply node of an associated one of the semiconductor devices, a differential amplifier circuit including a second output node coupled to a control electrode of the transistor, and a mirror capacitor coupled between the second output node of the differential amplifier and the output node thereof.