System, device and method for reducing cross-talk in differential signal conductor pairs
View Patent ↗Systems, devices and methods are disclosed herein for reducing crosstalk between pairs of differential signal conductors. One or more ground traces connected to one or more over- or under-lying ground planes by vias are located between pairs of differential signal conductors. The electrical shielding provided by the combination of the one or more ground traces and the one or more ground planes results in reduced cross-talk between different pairs of differential signal conductors, and facilitates high-speed data rates between integrated circuits and printed circuit boards. In a preferred embodiment, such ground traces and ground planes are employed in HiTCE packaging containing multiple pairs of differential signal conductors.
1. An integrated circuit package configured to reduce cross-talk and maintain constant impedance in first and second differential signal conductor pairs incorporated therein, comprising:
(a) a substrate;
(b) a first ground plane disposed below the substrate;
(c) a second ground plane disposed above the substrate;
(d) respective pairs of first and second differential signal conductors disposed within the substrate and substantially in a first plane; and
(e) a third pair of victim conductors disposed within the substrate and substantially in the first plane, the third pair of victim conductors further being disposed between the first and second pairs of differential signal conductors;
(f) at least first and second ground traces disposed in the substrate and substantially in the first plane, the first and second ground traces being disposed, respectively, between the first pair of differential signal conductors and the third pair of victim conductors, and between the second pair of differential signal conductors and the third pair of victim conductors, wherein the first and second ground traces are electrically connected to the first and second ground planes, and further wherein the widths of the first and second ground traces are varied along their respective routes within the substrate to maintain constant impedance in the first and second pairs of differential signal conductors.
2. The device of claim 1 , wherein a spacing between the first and second pairs of differential signal conductors is constant.
3. The device of claim 1 wherein a spacing between the first and second pairs of differential signal conductors changes.
4. The device of claim 3 , wherein the spacing changes to accommodate pitch differences.
5. The device of claim 4 wherein the pitch differences are associated with changes occurring between the integrated circuit package and a printed circuit board.
6. The device of claim 1 , wherein at least one of the first pair of conductors and the second pair of conductors has a trace heights ranging between about 2 μm and about 100 μm, between about 4 μm and about 80 μm, between about 6 μm and about 40 μm, between about 8 μm and about 20 μm, and between about 10 μm and about 14 μm.
7. The device of claim 1 , wherein the spacing between the first ground trace or the second ground trace and the first pair of conductors or the second pair of conductors ranges between about 10 μm and about 1000 μm, between about 20 μm and about 500 μm, between about 30 μm and about 250 μm, between about 40 μm and about 120 μm, or between about 60 μm and about 100 μm.
8. The device of claim 1 , wherein the spacing between the first ground plane and the second ground plane ranges between about 20 μm and about 1000 μm, between about 40 μm and about 500 μm, between about 60 μm and about 400 μm, between about 80 μm and about 200 μm, or between about 100 μm and about 160 μm.
9. The device of claim 1 , wherein at least one of the first pair of conductors and the second pair of conductors has a trace widths ranging between about 5 μm and about 200 μm, between about 20 μm and about 100 μm, between about 40 μm and about 80 μm, between about 50 μm and about 70 μm, and between about 55 μm and about 65 μm.
10. The device of claim 1 , wherein the spacing between the first ground plane and the second ground plane ranges between about 20 μm and about 1000 μm, between about 40 μm and about 500 μm, between about 60 μm and about 400 μm, between about 80 μm and about 200 μm, or between about 100 μm and about 160 μm.
11. The device of claim 1 , wherein the substrate comprises at least one of ceramic, HiTCE ceramic, high-temperature ceramic, high-temperature ETC ceramic, resin, glass, an electrically insulative material, and a dielectric material.
12. The device of claim 1 , wherein the integrated circuit package is a HiTCE package.
13. The device of claim 1 , wherein the integrated circuit package is configured for use in high-speed communications equipment.
14. The device of claim 1 , wherein the first and second pairs of differential signal conductors are formed from at least one of copper, a metal, a metal alloy, aluminum, gold, and silver.
15. The device of claim 1 , wherein a spacing between the first and second pairs of conductors increases along at least portions of the first plane.
16. The device of claim 1 , wherein the first or second ground trace has a width that increases as the spacing between the first and second pairs of conductors increases.
17. The device of claim 1 , wherein the first ground plane is electrically connected to the first ground trace or the second ground plane is electrically connected to the second ground trace along about every 0.35 mm of ground trace length, about every 0.5 mm of ground trace length, about every 0.84 mm of ground trace length, about every 1 mm of ground trace length, about every 3 mm of trace length, about every 4 mm of ground trace length, about every 5 mm of ground trace length, about every 6 mm of trace length, about every 8 mm of ground trace length, or about every 10 mm of trace length.
18. The device of claim 1 , wherein the impedance of the first and second differential signal conductor pairs ranges between about 50 ohms and about 150 ohms, or about 75 ohms and about 125 ohms.
19. A method of making an integrated circuit package configured to reduce cross-talk and maintain constant impedance in first and second differential signal conductor pairs incorporated therein, comprising providing a substrate, providing first and second ground planes disposed above and below the substrate, respectively, providing respective first and second pairs of first and second differential signal conductors disposed within the substrate and substantially in a first plane, providing a third pair of victim conductors disposed within the substrate and substantially in the first plane, the third pair of victim conductors further being disposed between the first and second differential signal conductor pairs; and providing first and second ground traces disposed, respectively, between the first pair of differential signal conductors and the third pair of victim conductors, and between the second pair of differential signal conductors and the third pair of victim conductors, wherein the first and second ground traces are electrically connected to the first and second ground planes, and further wherein the widths of the first and second ground traces are varied along their respective routes within the substrate to maintain constant impedance in the first and second pairs of differential signal conductors.
20. The method of claim 19 , further comprising maintaining a constant spacing between the first and second pairs of differential signal conductors.
21. The method of claim 19 , further comprising changing a spacing between the first and second pairs of differential signal conductors.
22. The method of claim 21 , wherein the spacing changes are configured to accommodate pitch differences.
23. The method of claim 22 , wherein the pitch differences are associated with changes occurring between the integrated circuit package and a printed circuit board.
24. The method of claim 19 , wherein the substrate comprises at least one of ceramic, high-temperature ceramic, high-temperature ETC ceramic, resin, glass, an electrically insulative material, and a dielectric material.
25. The method of claim 19 , wherein the integrated circuit package is a HiTCE package.
26. The method of claim 19 , wherein the integrated circuit package is configured for use in high-speed communications equipment.
27. The method of claim 19 , wherein a spacing between the first and second pairs of conductors increases along at least portions of the first plane.
28. The method of claim 27 , wherein the first or second ground trace has a width that increases as the spacing between the first and second pairs of conductors increases.