IP Library Assignment 030370/0092
Patent Assignment
Reel/Frame 030370/0092

Merger

Recorded: 2013-05-07 Pages: 3
Assignor
Assignee
AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
NO. 1 YISHUN AVENUE 7, SINGAPORE, 768923, SINGAPORE
Covered Properties (28)
Method and System for Routing Packets Through a Network by Employing Geographical Position Data
Patent: 7,307,978 →
Application: 09/847,765 →
Publication: US 2002/0163912
Inp Based High Temperature Lasers with Inasp Quantum Well Layers and Barrier Layers of Gax(Alln)1-Xp
Patent: 6,730,944 →
Application: 10/354,276 →
Alpha-Particle-Tolerant Semiconductor Die Systems, Devices, Components and Methods for Optimizing Clock Rates and Minimizing Die Size
Patent: 7,451,418 →
Application: 11/523,247 →
Publication: US 2007/0032065
System, Device and Method for Reducing Cross-Talk in Differential Signal Conductor Pairs
Patent: 7,609,125 →
Application: 11/580,444 →
Publication: US 2008/0088007
Apparatus and Method for Determining Capacitance Variation in an Integrated Circuit
Patent: 7,501,836 →
Application: 11/599,027 →
Publication: US 2008/0111562
Precision Phase Generator and Method for Phase Generation
Patent: 7,977,992 →
Application: 11/599,236 →
Publication: US 2008/0113642
Variable Delay Element
Patent: 7,545,195 →
Application: 11/599,237 →
Publication: US 2008/0111608
Apparatus and Method for Generating a Constant Logical Value in an Integrated Circuit
Patent: 7,741,879 →
Application: 11/677,902 →
Publication: US 2008/0204082
Bias Circuit for Common-Mode and Semiconductor Process Voltage and Temperature Optimization for a Receiver Assembly
Patent: 7,952,398 →
Application: 11/741,115 →
Publication: US 2008/0268804
High-Speed Receiver Assembly
Patent: 7,570,083 →
Application: 11/741,138 →
Publication: US 2008/0265986
System and Method for Equalizing Transition Density in an Integrated Circuit
Patent: 7,548,174 →
Application: 11/867,238 →
Publication: US 2009/0091369
Utilizing Serializer-Deserializer Transmit and Receive Pads for Parallel Scan Test Data
Patent: 7,739,567 →
Application: 12/037,157 →
Publication: US 2009/0217113
Internal Loop-Back Architecture for Parallel Serializer/Deserializer (Serdes)
Patent: 7,742,427 →
Application: 12/037,185 →
Publication: US 2009/0213913
Testing Phase Error of Multiple on-Die Clocks
Patent: 7,882,474 →
Application: 12/049,645 →
Publication: US 2009/0235218
Integrated Circuit Transmission Lines, Methods for Designing Integrated Circuits Using the Same and Methods to Improve Return Loss
Patent: 7,855,614 →
Application: 12/122,426 →
Publication: US 2009/0284324
System and Method for Backside Circuit Editing on Full Thickness Silicon Device
Patent: 8,133,760 →
Application: 12/470,680 →
Publication: US 2010/0297787
Circuits and Methods for Processing Memory Redundancy Data
Patent: 8,281,190 →
Application: 12/534,150 →
Publication: US 2011/0029813
Interfaces, Circuits, and Methods for Communicating with a Double Data Rate Memory Device
Patent: 8,234,422 →
Application: 12/557,658 →
Publication: US 2011/0063931
Methods for Efficiently Repairing Embedded Dynamic Random-Access Memory Having Marginally Failing Cells
Patent: 8,358,548 →
Application: 12/581,202 →
Publication: US 2011/0090751
Systems and Methods for Measuring Soft Errors and Soft Error Rates in an Application Specific Integrated Circuit
Patent: 8,145,959 →
Application: 12/604,643 →
Publication: US 2011/0099440
Rc-Based Delay Element and Method for Reducing Frequency Induced Delay Variation
Patent: 7,982,516 →
Application: 12/727,363 →
Method for Facilitating the Stacking of Integrated Circuits Having Different Areas and an Integrated Circuit Package Constructed by the Method
Patent: 8,174,108 →
Application: 12/730,947 →
Publication: US 2011/0233757
Memory Banking System and Method to Increase Memory Bandwidth via Parallel Read and Write Operations
Patent: 8,359,438 →
Application: 12/782,579 →
Publication: US 2011/0289256
Systems, Methods, and Programs for Leakage Power and Timing Optimization in Integrated Circuit Designs
Patent: 8,332,802 →
Application: 12/911,156 →
Publication: US 2012/0102448
Direct Cooling System and Method for Transceivers
Patent: 8,358,504 →
Application: 13/008,461 →
Publication: US 2012/0182688
Self-Contained Systems Including Scalable and Programmable Divider Architectures and Methods for Generating a Frequency Adjustable Clock Signal
Patent: 8,188,766 →
Application: 13/024,633 →
System and Method for Distribution Analysis of Stacked-Die Integrated Circuits
Patent: 8,352,896 →
Application: 13/036,364 →
Publication: US 2012/0221996
Circuits and Methods for Reducing Noise in the Power Supply of Circuits Coupled to a Bidirectional Bus
Patent: 8,279,697 →
Application: 13/281,303 →
Publication: US 2012/0039136
Related Assignments (25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Aug 29, 2001
From: CARLSON, GREG
To: AGILENT TECHNOLOGIES, INC.
Reel/Frame 011913/0165 →
Assignment of Assignor's Interest May 15, 2003
From: TANDON, ASHISH; CHANG, YING-LAN; CORZINE, SCOTT W.; BOUR, DAVID P.
To: AGILENT TECHNOLOGIES, INC.
Reel/Frame 013659/0050 →
Assignment of Assignor's Interest Feb 22, 2006
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP PTE. LTD.
Reel/Frame 017206/0666 →
Assignment of Assignor's Interest Feb 22, 2006
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP PTE. LTD.
Reel/Frame 017207/0020 →
Assignment of Assignor's Interest May 25, 2006
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES ENTERPRISE IP (SINGAPORE) PTE. LTD.
Reel/Frame 017675/0407 →
Assignment of Assignor's Interest Oct 23, 2006
From: PORTER, HOWARD L.; RODGERS, RICHARD S.; FRERICHS, TROY
To: AVAGO TECHNOLOGIES ENTERPRISE IP (SINGAPORE) PTE. LTD.
Reel/Frame 018422/0697 →
Assignment of Assignor's Interest Nov 20, 2006
From: QUACH, MING VAN; DEVNANI, NURWATI S.; MANLEY, ROBERT B.
To: AVAGO TECHNOLOGIES ENTERPRISE IP (SINGAPORE) PTE. LTD.
Reel/Frame 018538/0425 →
Assignment of Assignor's Interest Feb 7, 2007
From: HANSEN, JAMES E; HANSEN, ROBERT H; MILBURN, GREGORY J
To: AVAGO TECHNOLOGIES ENTERPRISE IP (SINGAPORE) PTE. LTD.
Reel/Frame 018865/0354 →
Assignment of Assignor's Interest Mar 12, 2007
From: FARMER, MICHAEL MARTIN
To: AVAGO TECHNOLOGIES IMAGING IP (SINGAPORE) PTE. LTD.
Reel/Frame 018996/0331 →
Assignment of Assignor's Interest Mar 12, 2007
From: FARMER, MICHAEL MARTIN
To: AVAGO TECHNOLOGIES IMAGING IP (SINGAPORE) PTE. LTD.
Reel/Frame 018996/0193 →
Assignment of Assignor's Interest May 26, 2007
From: SALCIDO, MANUEL; PATTERSON, J. KEN; CYNKAR, THOMAS EDWARD
To: AVAGO TECHNOLOGIES ENTERPRISE IP (SINGAPORE) PTE. LTD.
Reel/Frame 019347/0337 →
Assignment of Assignor's Interest May 26, 2007
From: MILLER, ROBERT HARRY, JR; YOH, GILBERT; MARTIN, ROBERT J
To: AVAGO TECHNOLOGIES ENTERPRISE IP (SINGAPORE) PTE. LTD.
Reel/Frame 019347/0294 →
Assignment of Assignor's Interest May 26, 2007
From: SALCIDO, MANUEL; GENTRY, MICHELLE MARIE; KORZYNIOWSKI, RYAN
To: AVAGO TECHNOLOGIES ENTERPRISE IP (SINGAPORE) PTE. LTD.
Reel/Frame 019347/0309 →
Assignment of Assignor's Interest Oct 11, 2007
From: FARMER, MICHAEL MARTIN; MARTIN, ROBERT J.; MEIER, PETER
To: AVAGO TECHNOLOGIES ENTERPRISE
Reel/Frame 019958/0973 →
Assignment of Assignor's Interest Feb 26, 2008
From: FARMER, MICHAEL MARTIN; MARTIN, ROBERT J.; MEIER, PETER
To: AVAGO TECHNOLOGIES ENTERPRISE IP (SINGAPORE) PTE. LTD.
Reel/Frame 020560/0256 →
Assignment of Assignor's Interest Feb 26, 2008
From: VANDIVIER, SUZETTE D.; VOLZ, AARON M.
To: AVAGO TECHNOLOGIES ENTERPRISE IP (SINGAPORE) PTE. LTD.
Reel/Frame 020558/0620 →
Assignment of Assignor's Interest Mar 17, 2008
From: WAHL, MARK A.; VOLZ, AARON M.; DORNER, KRISTA R.
To: AVAGO TECHNOLOGIES ENTERPRISE IP (SINGAPORE) PTE. LTD.
Reel/Frame 020661/0144 →
Assignment of Assignor's Interest May 16, 2008
From: VAN QUACH, MINH; DEVNANI, NURWATI S.; LIN, WANG; TOK, HYACINTH
To: AVAGO TECHNOLOGIES ECBU IP PTE. LTD.
Reel/Frame 020961/0695 →
Assignment of Assignor's Interest May 22, 2009
From: NILES, DAVID WINSLOW, MR.; KEE, RONALD WILLIAM, MR.
To: AVAGO TECHNOLOGIES ENTERPRISE IP (SINGAPORE) PTE. LTD.
Reel/Frame 022725/0289 →
Assignment of Assignor's Interest Aug 3, 2009
From: GUNDERSON, ROSALEE; BEUCLER, DALE; KOSS, LOUISE A.
To: AVAGO TECHNOLOGIES ENTERPRISE IP PTE. LTD.
Reel/Frame 023041/0214 →
Assignment of Assignor's Interest Aug 17, 2009
From: MARVELL INTERNATIONAL TECHNOLOGY LTD.
To: AVAGO TECHNOLOGIES ENTERPRISE IP (SINGAPORE) PTE. LTD.
Reel/Frame 023105/0625 →
Assignment of Assignor's Interest Feb 9, 2011
From: AVAGO TECHNOLOGIES IMAGING IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES ENTERPRISE IP (SINGAPORE) PTE. LTD.
Reel/Frame 025784/0304 →
Assignment of Assignor's Interest May 27, 2011
From: AVAGO TECHNOLOGIES ECBU IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES ENTERPRISE IP (SINGAPORE) PTE. LTD.
Reel/Frame 026353/0781 →
Patent Security Agreement May 8, 2014
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032851/0001 →
Termination and Release of Security Interest in Patent Rights (Releases Rf 032851-0001) Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 037689/0001 →