Precision phase generator and method for phase generation
View Patent ↗A phase generator includes a delay element configured to receive an input signal and delay the input signal by a predetermined amount to develop a delayed version of the input signal, a logic element configured to receive the input signal and the delayed version of the input signal, the logic element configured to produce a signal dependent on a phase difference between the input signal and the delayed version of the input signal, a circuit configured to generate a reference signal, and a comparator configured to receive an output of the logic element and the reference signal. The comparator is configured to generate a control signal that is dependent on the difference between the output of the logic element and the reference signal, where the control signal is applied to the delay element to determine the delay applied to the input signal.
1. A phase generator, comprising:
a delay element configured to receive an input signal and configured to delay the input signal by a predetermined amount to develop a delayed version of the input signal;
a logic element configured to receive the input signal and the delayed version of the input signal, the logic element configured to produce a signal dependent on a phase difference between the input signal and the delayed version of the input signal;
a circuit configured to generate an analog reference signal independent of an output of the logic element and having a fixed amplitude;
an analog amplitude comparator configured to receive the output of the logic element and the analog reference signal, the analog amplitude comparator configured to generate a control signal that is dependent on the amplitude difference between the output of the logic element and the analog reference signal, where the control signal is applied to the delay element to determine the delay applied to the input signal; and
a frequency detector configured to affect the control signal in response to the delay between the input signal and the delayed version of the input signal.
2. The phase generator of claim 1 , wherein the analog reference signal determines the predetermined delay applied to the input signal.
3. The phase generator of claim 1 , wherein the frequency detector is configured to reset the delay element when the delay between the input signal and the delayed version of the input signal reaches 180 degrees.
4. The phase generator of claim 1 , wherein the output of the logic element is a signal having a duty cycle that corresponds to a difference in phase between the input signal and the delayed version of the input signal.
5. The phase generator of claim 2 , wherein the logic element is an exclusive OR logic gate.
6. The phase generator of claim 2 , wherein the circuit configured to generate an analog reference signal further comprises a voltage divider.
7. The phase generator of claim 6 , wherein the voltage divider further comprises at least two resistances, the value of the resistances determining a level of the reference signal.
8. A method for generating multiple phases of an input signal, the method comprising:
providing an input signal having at a first phase;
delaying the input signal by a predetermined amount to develop a delayed version of the input signal;
providing the input signal and the delayed version of the input signal to a logic element, the logic element developing a signal that is dependent on a phase difference between the input signal and the delayed version of the input signal;
generating an analog reference signal independent of an output of the logic element and having a fixed amplitude;
comparing an amplitude of the output of the logic element and an amplitude of the analog reference signal;
generating a control signal that is dependent on the amplitude difference between the output of the logic element and the analog reference signal;
applying the control signal to determine the delay applied to the input signal; and
affecting the control signal in response to the delay between the input signal and the delayed version of the input signal.
9. The method of claim 8 , wherein the analog reference signal determines the predetermined delay applied to the input signal.
10. The method of claim 8 , wherein affecting the control signal resets the delayed version of the input signal when the delay between the input signal and the delayed version of the input signal reaches 180 degrees.
11. The method of claim 8 , wherein the output of the logic element is a signal having a duty cycle that corresponds to a difference in phase between the input signal and the delayed version of the input signal.
12. The method of claim 8 , further comprising implementing the logic element as an exclusive OR logic gate.
13. The method of claim 9 , further comprising implementing the circuit configured to generate a reference signal as a voltage divider.
14. A circuit for generating multiple phase signals, comprising:
a variable delay element configured to receive an input signal and configured to delay the input signal by a predetermined amount to develop at least one delayed version of the input signal;
a logic element configured to receive the input signal and the at least one delayed version of the input signal, the logic element configured to produce a signal dependent on a phase difference between the input signal and the at least one delayed version of the input signal;
a voltage divider configured to generate an analog reference signal independent of an output of the logic element and having a fixed amplitude;
an analog amplitude comparator configured to receive the output of the logic element and the analog reference signal, the analog amplitude comparator configured to generate a control signal that is dependent on the amplitude difference between the output of the logic element and the analog reference signal, where the control signal is applied to the variable delay element to determine the delay applied to the input signal; and
a frequency detector configured to affect the control signal in response to the delay between the input signal and the delayed version of the input signal.
15. The circuit of claim 14 , wherein the analog reference signal determines the predetermined delay applied to the input signal.
16. The circuit of claim 14 , wherein the frequency detector is configured to reset the variable delay element when the delay between the input signal and the delayed version of the input signal reaches 180 degrees.
17. The circuit of claim 14 , wherein the output of the logic element is a signal having a duty cycle that corresponds to a difference in phase between the input signal and the at least one delayed version of the input signal.
18. The circuit of claim 14 , wherein the logic element is an exclusive OR logic gate.
19. The circuit of claim 14 , wherein the voltage divider further comprises at least two resistances, the value of the resistances determining a level of the analog reference signal.
20. The circuit of claim 14 , wherein the output of the logic element is a signal having a frequency that is twice a frequency of the input signal and the at least one delayed version of the input signal.