Testing phase error of multiple on-die clocks
View Patent ↗The phase relationship between two clock signals in an integrated circuit (IC) is determined by transforming each of the clock signals into a data word, where bit transitions in the data word represent signal transitions in the clock signal, and comparing the two data words. For example, in an IC having a de-serializer as part of its input/output logic, the clocks are sequentially multiplexed into the de-serializer, which transforms the clocks into parallel-format data words. The resulting words corresponding to the first and second clock signals can then be compared to determine clock signal transition differences and thus the phase relationship between the corresponding clocks signals.
1. An integrated circuit, comprising:
input/output (I/O) logic having output logic operating under a second clock signal to receive data from core logic to be output from the IC, the I/O logic including de-serializer logic, the de-serializer logic having multiplexing logic with a serial-format data input to receive data input to the IC, a first clock signal input, and a second clock signal input;
clock phase test control logic coupled to a selector input of the multiplexing logic, the clock phase test control logic causing the multiplexing logic to select the first clock signal input, wherein the de-serializer logic produces parallel-format first clock data representing the first clock signal received from the multiplexing logic, and the clock phase test control logic causing the multiplexing logic to select the second clock signal input, wherein the de-serializer logic produces parallel-format second clock data representing the second clock signal received from the multiplexing logic; and
comparison logic coupled to the de-serializer logic, the comparison logic comparing the parallel-format first clock data with the parallel-format second clock data in a bitwise comparison to determine clock signal transition differences represented by bit differences between the parallel-format first clock data and the parallel-format second clock data.
2. The integrated circuit claimed in claim 1 , wherein:
the de-serializer logic is a de-serializer portion of a Serializer/De-serializer (SerDes), and the multiplexing logic has a serial-format data input to receive data input to the IC, a first clock signal input, a second clock signal input, and a loopback data input coupled to the core logic via a serializer portion of the SerDes; and
the de-serializer portion of the SerDes synchronizes itself to a synchronization pattern received from the core logic via the serializer portion of the SerDes.
3. The integrated circuit claimed in claim 1 , wherein the comparison logic is included in the core logic.