Granted Patent B2

US 7,742,427 · App. 12/037,185 · Granted Jun 22, 2010

Abstract

Claims (25)

1. An internal loop-back architecture for a parallel serializer/deserializer (SERDES), comprising:

a transmitter macro including a plurality of transmit elements arranged in a parallel architecture; and a receiver macro including a plurality of receive elements arranged in a parallel architecture, wherein at least a portion of the transmit elements and a portion of the receive elements share a communication channel and wherein any of the plurality of transmit elements in a row can communicate with any of the plurality of receive elements in a row, and

wherein each of the plurality of transmit elements includes a loop-back arrangement with each of the plurality of receive elements, and

wherein the plurality of transmit elements are individually addressable in a row and column arrangement; and the plurality of receive elements are individually addressable in a row and column arrangement, wherein adjoining transmit elements in a row are coupled together to access the communication channel and wherein adjoining receive elements in a row are coupled together to access the communication channel.

2. The architecture of claim 1 , in which the communication channel between a selected transmit element and a selected receive element includes a forward path and a reverse path.

3. The architecture of claim 2 , in which the communication channel between a transmit element and a receive element includes a forward clock signal.

4. The architecture of claim 3 , in which a signal can be sent from one of the transmit elements to simultaneously test all of the receive elements.

5. The architecture of claim 3 , in which a signal can be sent from a selected transmit element to a selected receive element and then sent from the selected receive element back to the selected transmit element in a loop-back arrangement.

6. The architecture of claim 5 , in which the signal can be sent out of the selected transmit element for observation.

7. The architecture of claim 3 , in which the signal can be sent from a selected receive element to a selected transmit element and then be sent out of the selected transmit element for observation.

8. An internal loop-back architecture for a parallel serializer/deserializer (SERDES), comprising:

a plurality of transmitters arranged in a parallel architecture in which adjoining transmitters can communicate with each other; and a plurality of receivers arranged in a parallel architecture in which adjoining receivers can communicate with each other, wherein at least a portion of the transmitters and a portion of the receivers share a communication channel and wherein any of the plurality of transmitters in a row can communicate with any of the plurality of receivers in a row, and

wherein each of the plurality of transmitters includes a loop-back arrangement with each of the plurality of receivers, and

wherein the plurality of transmitters are individually addressable in a row and column arrangement; and the plurality of receivers are individually addressable in a row and column arrangement, wherein adjoining transmitters in row are coupled together to access the communication channel and wherein adjoining receivers in a row are coupled together to access the communication channel.

9. The architecture of claim 8 , in which the communication channel between a selected transmitter and a selected receiver includes a forward path and a reverse path.

10. The architecture of claim 8 , in which the communication channel between a transmitter and a receiver includes a forward clock signal.

11. The architecture of claim 8 , in which a signal can be sent from one of the transmitters to simultaneously test all of the receivers.

12. A method for performing internal loop-back testing on a serializer/deserializer (SERDES), comprising:

coupling a plurality of transmit elements arranged in a parallel architecture with a plurality of receive elements arranged in a parallel architecture such that at least a portion of the transmit elements and a portion of the receive elements share a communication channel and such that any of the plurality of transmit elements in a row can communicate with any of the plurality of receive elements in a row, and

such that each of the plurality of transmit elements includes a loop-back arrangement with each of the plurality of receive elements, and

such that the plurality of transmit elements are individually addressable in a row and column arrangement; and the plurality of receive elements are individually addressable in a row and column arrangement, wherein the method comprises coupling adjoining transmit elements in a row to access the communication channel and coupling adjoining receive elements in a row to access the communication channel.

13. The method of claim 12 , in which the communication channel between a selected transmit element and a selected receive element includes a forward path and a reverse path.

14. The method of claim 13 , further comprising providing a forward clock signal between a transmit element and a receive element.

15. The method of claim 14 , further comprising sending a signal from one of the transmit elements to simultaneously test all of the receive elements.

16. The method of claim 14 , further comprising sending a signal from a selected transmit element to a selected receive element and then sent from the selected receive element back to the selected transmit element in a loop-back arrangement.

Assignments (11)