Method for facilitating the stacking of integrated circuits having different areas and an integrated circuit package constructed by the method
View Patent ↗An integrated circuit package comprises a package substrate, an application specific integrated circuit (ASIC) having a first area and formed on a first wafer made from a select semiconductor material, a second wafer of the select semiconductor material, and a supplemental-integrated circuit. The supplemental-integrated circuit has a second area different from the first area. The first wafer includes a through-wafer via to couple the ASIC to the package substrate. An active surface of the ASIC is coupled to the second wafer. The second wafer is arranged with a window there through that is sized to closely receive and align one or more bonding interfaces of the supplemental-integrated circuit to respective bonding interfaces of the ASIC. A corresponding method for assembling a die-stacked integrated circuit package is disclosed.
1. An integrated circuit package, comprising:
an application specific integrated circuit having a first area on an active surface of a first wafer, the first wafer comprising a select semiconductor material and at least one through wafer via;
a second wafer having a circuit surface coupled to the application specific integrated circuit, the circuit surface of the second wafer coupled to a circuit device that operates with a supply voltage that is different in voltage than an application specific integrated circuit supply voltage coupled to the application specific integrated circuit and a second supply voltage coupled to a supplemental-integrated circuit, the second wafer of the select semiconductor material having at least one window there through, the window sized to closely receive the supplemental-integrated circuit different from the application specific integrated circuit and having a second area different from the first area, the supplemental-integrated circuit further having a respective active surface arranged such that a first conductor on the respective active surface is in registration with a corresponding conductor of the application specific integrated circuit; and
a package substrate coupled to the application specific integrated circuit by the at least one through wafer via.
2. The integrated circuit package of claim 1 , wherein the circuit surface of the second wafer is manufactured using a less expensive manufacturing process than that used to produce either the application specific integrated circuit or the supplemental-integrated circuit.
3. The integrated circuit package of claim 1 , further comprising:
a thermally conductive interface material in contact with an opposed surface of the second wafer and a backside surface opposed to the respective active surface of the supplemental-integrated circuit; and
a heat sink in contact with the thermally conductive interface material.
4. The integrated circuit package of claim 1 , wherein the circuit surface of the second wafer is bonded to the application specific integrated circuit.
5. The integrated circuit package of claim 1 , wherein the circuit surface of the second wafer is soldered to the application specific integrated circuit.
6. The integrated circuit package of claim 1 , wherein the second wafer is coupled to the application specific integrated circuit in a batch process.
7. The integrated circuit package of claim 1 , wherein the first wafer comprises a first index mark.
8. The integrated circuit package of claim 1 , wherein the second wafer comprises a second index mark.
9. The integrated circuit package of claim 1 , wherein a first manufacturing technique used to form circuit elements in the supplemental integrated circuit is different from a second manufacturing technique used to form circuit elements on the second wafer.
10. The integrated circuit package of claim 1 , wherein multiple connections transfer heat away from the application specific integrated circuit.
11. The integrated circuit package of claim 1 , wherein the package substrate comprises a base surface.
12. The integrated circuit package of claim 11 , further comprising a heat sink in thermal contact with the substrate by way of the base surface.
13. The integrated circuit package of claim 12 , further comprising a mechanically compliant thermally conductive material disposed between the base surface and the heat sink.