System and method for distribution analysis of stacked-die integrated circuits
View Patent ↗Systems and methods for distribution analysis of a stacked-die integrated circuit (IC) are described. The stacked-die integrated circuit includes a primary die, and clock load information for the primary die of the IC is determined. Additionally, a clock load model may be created using the clock load information for the primary die. Clock load information for a second die that is coupled to the primary die may also be determined. The clock load information for the second die may be incorporated into the clock load model to create an enhanced clock load model of the stacked-die IC, which may then be analyzed as if a single-die IC.
1. A method for distribution analysis of a stacked-die integrated circuit (IC), the method comprising:
in one or more processors:
analyzing clock distribution load information for a primary die of the IC to create a first clock distribution load model for the primary die of the IC;
analyzing clock distribution load information for a second die of the IC that is coupled to the primary die to create a second clock distribution load model for the second die of the IC;
projecting the clock distribution load information of the second clock distribution load model onto the first clock distribution load model to create an enhanced clock load model; and
analyzing the enhanced clock distribution load model to identify clock distribution load issues of the IC.
2. The method of claim 1 , wherein the clock distribution load information for the second die of the IC comprises clock distribution load information for at least one component of the second die to be clocked to at least one component of the primary die.
3. The method of claim 2 , wherein the clock distribution load information for the second die of the IC further comprises clock distribution load information for a clock signal distribution path to the at least one component of second die.
4. The method of claim 3 , wherein the clock signal distribution path further comprises a solder bump between the primary die and the second die.
5. The method of claim 1 , further comprising:
analyzing clock distribution load information for a third die of the IC that is coupled to the primary die to create a third clock distribution load model for the third die of the IC; and
projecting the clock distribution load information of the third clock distribution load model onto the first and second clock distribution load models to create the enhanced clock load model.
6. The method of claim 1 , further comprising:
analyzing clock distribution load information for a third die of the IC that is coupled to the second die to create a third clock distribution load model for the third die of the IC; and
projecting the clock distribution load information of the third clock distribution load model onto the first and second clock distribution load models to create the enhanced clock load model.
7. The method of claim 1 , wherein the primary die comprises at least one of a processor, DRAM, Flash memory, ROM, EEPROM, RAM, field-programmable gate array, or analog component.
8. The method of claim 1 , wherein the second die comprises at least one of a processor, DRAM, Flash memory, ROM, EEPROM, RAM, field-programmable gate array, or analog component.
9. A method for distribution analysis of a stacked-die integrated circuit (IC), the method comprising:
in one or more processors:
analyzing clock distribution load information for a primary die of the IC to create a first clock distribution load model for the primary die of the IC;
analyzing the first clock distribution load model to determine if the clock distribution load information in the first clock distribution load model exceeds a threshold value;
redesigning a portion of the primary die if the clock distribution load information exceeds the threshold value;
analyzing clock distribution load information for at least a second die of the IC that is coupled to the primary die to create a second clock distribution load model for the second die of the IC;
projecting the clock distribution load information of the second clock distribution load model onto the first clock distribution load model to create an enhanced clock load model; and
analyzing the enhanced clock distribution load model to determine if the clock distribution load information in the enhanced clock load'model exceeds the threshold value.
10. The method of claim 9 , further comprising:
redesigning a portion of the primary die when the clock distribution load information in the enhanced clock load model exceeds the threshold value.
11. The method of claim 9 , further comprising:
redesigning a portion of the second die when the clock distribution load information in the enhanced clock load model exceeds the threshold value.
12. The method of claim 9 , further comprising:
analyzing clock distribution load information for at least a third die of the IC that is coupled to the primary die; and
projecting the clock distribution load information for the third die into the first clock distribution load model to create the enhanced clock load model.
13. The method of claim 12 , wherein the step of analyzing the clock distribution load information for the third die of the IC further comprises: creating a third-die clock distribution load model for the third die using the clock load information for the third die.
14. The method of claim 9 , further comprising:
analyzing clock distribution load information for at least a third die of the IC that is coupled to the second die; and
projecting the clock distribution load information for the third die into the first clock distribution load model to create the enhanced clock load model.
15. The method of claim 13 , further comprising:
redesigning a portion of the third die when the clock distribution load information in the enhanced clock load model exceeds the threshold value.