IP Library Granted Patent US 8,133,760
Granted Patent B2
US 8,133,760 · App. 12/470,680 · Granted Mar 13, 2012

System and method for backside circuit editing on full thickness silicon device

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Quick Facts
Patent No.
US 8,133,760
App. No.
12/470,680
Granted
Mar 13, 2012
Kind
B2
Abstract

A system for accessing circuitry on a flip chip circuit device with active circuitry and full-thickness bulk silicon includes a moveable surface for supporting and locating the circuit device in a plane, an infrared (IR) imaging device located at a defined perpendicular distance from a surface of the bulk silicon, the surface of the bulk silicon parallel to the plane and a milling chamber configured to direct an etchant and a focused ion beam to the surface of the bulk silicon, resulting in a gas-enhanced milling process that creates a milled cavity in the bulk silicon. The system produces an IR reflective material located at a base of the cavity, wherein the circuit device is located within a field of view of the IR imaging device such that the IR reflective material is brought into focus by moving the IR imaging device an adjustable distance perpendicular to the surface of the bulk silicon, and where the adjustable perpendicular distance is indicative of a depth of the cavity.

Claims (37)

1. A system for accessing circuitry on a silicon device, comprising:

a flip chip circuit device comprising active circuitry and full-thickness bulk silicon;

a moveable surface for supporting and locating the circuit device in a plane;

an infrared (IR) imaging device located at a defined perpendicular distance from a surface of the bulk silicon, the surface of the bulk silicon parallel to the plane;

a milling chamber configured to direct an etchant and a focused ion beam to the surface of the bulk silicon, the etchant and the focused ion beam capable of creating a milled cavity in the bulk silicon;

an IR reflective material located at a base of the cavity; and

wherein the circuit device is located within a field of view of the IR imaging device such that the IR reflective material is brought into focus by moving the IR imaging device an adjustable distance perpendicular to the surface of the bulk silicon, and where the adjustable perpendicular distance is indicative of a depth of the cavity.

2. The system of claim 1 , wherein the IR reflective material is gallium.

3. The system of claim 1 , wherein the IR reflective material is gallium applied using a focused ion beam.

4. The system of claim 1 , wherein the IR reflective material is gallium applied using a focused ion beam and creates a pattern at the base of cavity, the pattern approximately 5 micrometers (μm) by 5 μm.

5. The system of claim 1 , wherein the IR imaging device focuses on the IR reflective material within a range of approximately ±2.5 micrometers (μm).

6. A method for accessing circuitry on a full thickness, flip-chip silicon device, the method comprising:

locating a circuit device comprising active circuitry and bulk silicon proximate to a gas-enhanced milling source;

locating an infrared (IR) imaging device at a defined perpendicular distance from a surface of the bulk silicon;

gas-enhanced milling the surface of the bulk silicon for a predetermined duration to create a cavity in the bulk silicon;

creating an IR reflective material at a base of the cavity;

locating the circuit device within a field of view of the IR imaging device;

focusing the IR imaging device on the IR reflective material by moving the IR imaging device an adjustable distance perpendicular to the surface of the bulk silicon; and

determining a depth of the cavity by measuring the adjustable perpendicular distance.

7. The method of claim 6 , further comprising computing a gas-enhanced milling rate by dividing the adjustable perpendicular distance by the predetermined duration.

8. The method of claim 6 , wherein the creating an IR reflective material comprises applying gallium.

9. The method of claim 6 , wherein the creating an IR reflective material comprises applying gallium using a focused ion beam.

10. The method of claim 6 , wherein the creating an IR reflective material comprises applying gallium using a focused ion beam to form a pattern at the base of cavity, the pattern approximately 5 micrometers (μm) by 5 μm.

11. The method of claim 6 , wherein the focusing the IR imaging device on the IR reflective material comprises focusing within a range of approximately ±2.5 micrometers (μm).

12. A method for determining gas-enhanced milling depth in silicon, the method comprising:

locating bulk silicon proximate to a gas-enhanced milling source;

locating an infrared (IR) imaging device at a defined perpendicular distance from a surface of the bulk silicon;

gas-enhanced milling the surface of the bulk silicon for a predetermined duration to create a cavity in the bulk silicon;

creating an IR reflective material at a base of the cavity;

locating the cavity within a field of view of the IR imaging device;

focusing the IR imaging device on the IR reflective material by moving the IR imaging device an adjustable distance perpendicular to the surface of the bulk silicon; and

determining a depth of the cavity by measuring the adjustable perpendicular distance.

13. The method of claim 12 , further comprising computing a gas-enhanced milling rate by dividing the adjustable perpendicular distance by the predetermined duration.

14. The method of claim 12 , wherein the creating an IR reflective material comprises applying gallium.

15. The method of claim 12 , wherein the creating an IR reflective material comprises applying gallium using a focused ion beam.

16. The method of claim 12 , wherein the creating an IR reflective material comprises applying gallium using a focused ion beam to form a pattern at the base of cavity, the pattern approximately 5 micrometers (μm) by 5 μm.

17. The method of claim 12 , wherein the focusing the IR imaging device on the IR reflective material comprises focusing within a range of approximately ±2.5 micrometers (μm).

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 09/05/2018 PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0133. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0456 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0133 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032851-0001) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 037689/0001 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032851/0001 →
MERGER Recorded May 7, 2013
From: AVAGO TECHNOLOGIES ENTERPRISE IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 030370/0092 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 22, 2009
From: NILES, DAVID WINSLOW, MR.; KEE, RONALD WILLIAM, MR.
To: AVAGO TECHNOLOGIES ENTERPRISE IP (SINGAPORE) PTE. LTD.
Reel/Frame 022725/0289 →