IP Library Granted Patent US 8,358,548
Granted Patent B2
US 8,358,548 · App. 12/581,202 · Granted Jan 22, 2013

Methods for efficiently repairing embedded dynamic random-access memory having marginally failing cells

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,358,548
App. No.
12/581,202
Granted
Jan 22, 2013
Kind
B2
Abstract

A test system and a method for efficiently repairing marginally failing memory cells in an embedded dynamic random access memory on an integrated circuit identify marginally failing cells in the embedded memory and when two or more marginally failing cells are located in the same column, indicating a partial column failure due to a weak sense amplifier associated with the column, the system and method apply a spare column preferentially to repair the failing cells in the column. The test system can be arranged in a built-in self test engine on the integrated circuit. In an alternative embodiment, the test system can be implemented in test equipment coupled to the integrated circuit that houses the embedded dynamic random-access memory.

Claims (32)

1. A method for efficiently repairing embedded dynamic random-access memory having marginally failing cells, the method comprising:

identifying a number of available redundant columns and a number of available redundant rows;

setting a respective flag representing a state of repairability for each of a column and a row;

applying a test pattern to a memory under test to identify failed cells;

for each failed cell, recording a column address;

decreasing a supply voltage by a predetermined voltage;

identifying any additional failed cells in a column identified by the column address, wherein when an additional cell failure is identified in the column, marking the column for repair;

decrementing the number of available redundant columns;

incrementing the supply voltage by the predetermined voltage;

repairing any column marked for repair;

applying the test pattern to the memory under test to identify failed cells;

for each failed cell, recording a row address;

identifying any additional failed cell in a row identified by the row address, wherein when an additional cell failure is identified in the row, marking the row for repair;

decrementing the number of available redundant rows;

repairing any row marked for repair;

applying the test pattern to the memory under test to identify failed cells;

for each failed cell, use a redundant row to repair the failed cell;

decrementing the number of available redundant rows until the available redundant rows are exhausted, wherein when available redundant columns have not been exhausted, using a redundant column to repair the failed cell and decrementing the number of available redundant columns.

2. The method of claim 1 , further comprising:

after decrementing the number of available redundant columns, determining if the supply of redundant columns is exhausted; and

when the supply of redundant columns is exhausted, changing the status of the flag representing the state of repairability for a column.

3. The method of claim 1 , further comprising:

after decrementing the number of available redundant rows, determining if the supply of redundant rows is exhausted; and

when the supply of redundant rows is exhausted, changing the status of the flag representing the state of repairability for a row.

4. The method of claim 1 , wherein the step of identifying any additional failed cells in a column identified by the column address comprises an incremental check of each row until a maximum number of rows.

5. The method of claim 1 , wherein the step of identifying any additional failed cells in a row identified by the row address comprises an incremental check of each column until a maximum number of columns.

6. The method of claim 1 , further comprising:

determining the status of the respective flags representing the state of repairability for each of a column and a row; and when the status of the respective flags indicates that available redundant columns and available redundant rows have been exhausted and failed cells remain, terminating the method.

7. The method of claim 6 , further comprising:

associating a failed status with the embedded dynamic random-access memory.

8. The method of claim 7 , further comprising:

scrapping an integrated circuit which includes the embedded dynamic random-access memory.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM INTERNATIONAL PTE. LTD.
Reel/Frame 053771/0901 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 09/05/2018 PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0133. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0456 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0133 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032851-0001) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 037689/0001 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032851/0001 →
MERGER Recorded May 7, 2013
From: AVAGO TECHNOLOGIES ENTERPRISE IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 030370/0092 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 19, 2009
From: MANNA, INDRAJIT; PFIESTER, JAMES; LEARY, DAVID
To: AVAGO TECHNOLOGIES ENTERPRISE IP PTE. LTD.
Reel/Frame 023387/0314 →