Utilizing serializer-deserializer transmit and receive pads for parallel scan test data
View Patent ↗A Serializer/De-serializer (SerDes) of an integrated circuit (IC) includes selectable inputs and outputs not only for functional data and boundary scan (e.g., JTAG) test data, but also for parallel-scan test data. The serializing portion of the SerDes includes multiplexing logic responsive to control signals to select or identify one of the multiplexing logic inputs for functional data, boundary scan data and parallel-scan data. The de-serializing portion similarly includes selection logic responsive to such control signals to select or identify one of the selection logic outputs for functional data, boundary scan data and parallel-scan data. The multiplexing logic and selection logic couple the selected input or output, respectively, to the SerDes input/output pads.
1. An integrated circuit, comprising:
functional logic relating to a primary function of the integrated circuit;
parallel-scan chain logic for integrated circuit structural testing;
boundary scan logic for boundary scan testing; and
serializer/de-serializer (SerDes) logic, the SerDes logic comprising serializer logic and de-serializer logic, the serializer logic comprising multiplexing logic responsive to control signals, and the de-serializer logic comprising selection logic responsive to the control signals, wherein:
the multiplexing logic couples a first multiplexing logic input to the functional logic to receive functional data in response to a first control signal state;
the multiplexing logic couples a second multiplexing logic input to the boundary scan logic to receive boundary scan data in response to a second control signal state;
the multiplexing logic couples a third multiplexing logic input to the parallel-scan chain logic to receive parallel-scan data in response to a third control signal state;
the selection logic couples a first selection logic output to the functional logic to provide functional data in response to the first control signal state;
the selection logic couples a second selection logic output to the boundary scan logic to provide boundary scan data in response to the second control signal state; and
the selection logic couples a third selection logic output to the parallel-scan logic to provide parallel-scan data in response to the third control signal state;
at least one serial data output pad element coupled to an output of the multiplexing logic; and
at least one serial data input pad element coupled to an input of the selection logic.
2. The integrated circuit claimed in claim 1 , wherein:
the serial data output pad element comprises a pair of differential output pads; and
the serial data input pad element comprises a pair of differential input pads.
3. The integrated circuit claimed in claim 2 , wherein:
the third selection logic output defines a first parallel-scan data input coupleable to a first one of the differential input pads in response to the third control signal state; and
the third selection logic output defines a second parallel-scan data input coupleable to a second one of the differential input pads in response to the third control signal state.
4. A method for serial data input and output in an integrated circuit (IC) having serializer/de-serializer (SerDes) logic, the SerDes logic comprising serializing logic having multiplexing logic and de-serializing logic having selection logic, the multiplexing logic and selection logic responsive to control signals, the method comprising:
receiving a control signal state represented by a combination of the control signals;
the multiplexing logic coupling a first multiplexing logic input to the functional logic to receive functional data in response to a first control signal state;
the multiplexing logic coupling a second multiplexing logic input to the boundary scan logic to receive boundary scan data in response to a second control signal state;
the multiplexing logic coupling a third multiplexing logic input to the parallel-scan chain logic to receive parallel-scan data in response to a third control signal state;
the selection logic coupling a first selection logic output to the functional logic to provide functional data in response to the first control signal state;
the selection logic coupling a second selection logic output to the boundary scan logic to provide boundary scan data in response to the second control signal state; and
the selection logic coupling a third selection logic output to the parallel-scan logic to provide parallel-scan data in response to the third control signal state.
5. The method claimed in claim 4 , wherein:
the third selection logic output defines a first parallel-scan data input, and the third selection logic couples the first parallel-scan data input to a first input pad of a pair of differential input pads in response to the third control signal state; and
the third selection logic output defines a second parallel-scan data input, and the third selection logic couples the second parallel-scan data input to a second input pad of the pair of differential input pads in response to the third control signal state.