Apparatus and method for determining capacitance variation in an integrated circuit
View Patent ↗An apparatus for determining capacitance variation in an integrated circuit, includes at least two capacitances, a stimulus provided to the at least two capacitances, and a first logic element coupled to the stimulus and the at least two capacitances, the first logic element configured to switch state upon a state transition of the stimulus when the at least two capacitances differ in value by a predetermined amount.
1. A capacitance variation determination circuit incorporated into an integrated circuit, comprising:
at least first and second parasitic capacitances, the first parasitic capacitance being associated with a first portion of the integrated circuit and having a first capacitance value associated therewith, the second parasitic capacitance being associated with a second portion of the integrated circuit and having a second capacitance value associated therewith;
means for providing a transient stimulus signal to the capacitance variation determination circuit and the at least first and second parasitic capacitances;
a first logic element operably coupled to the at least first and second parasitic capacitances, the first logic element being configured to switch state: (a) upon detecting the transient stimulus signal, and (b) when a difference between the first and second values exceeds a predetermined amount, and
means, operably coupled to the first logic element, for providing an output signal indicative of whether the difference exceeds the predetermined amount.
2. The apparatus of claim 1 ,
wherein the output signal providing means comprises a second logic element coupled to the first logic element, the second logic element being configured to change state upon the state transition of the first logic element.
3. The apparatus of claim 1 , wherein the first logic element is an exclusive NOR gate.
4. The apparatus of claim 1 , wherein when the difference exceeds the predetermined amount, and an anomaly at the inputs to the first logic element causes the first logic element to transition state.
5. The apparatus of claim 1 , further comprising a third logic element coupled to the inputs of the first logic element, the third logic element being configured to determine a phase difference between the inputs to the first logic element.
6. The apparatus of claim 5 , wherein the phase difference between the inputs to the first logic element is indicative of which of the at least first and second capacitances is larger.
7. The apparatus of claim 1 , wherein the first and second parasitic capacitances are generated by data lines, circuit traces or circuit components.
8. A method for determining parasitic capacitance variation in first and second portions of an integrated circuit, comprising:
providing at least first and second parasitic capacitances corresponding to the first and second portions of the integrated circuit, the first and second parasitic capacitances having first and second capacitance values associated therewith, respectively;
providing a transient stimulus signal to the at least first and second parasitic capacitances;
coupling a first logic element to the transient stimulus signal and to the at least first and second parasitic capacitances;
causing the first logic element to switch state: (a) upon detecting the transient stimulus signal, and (b) when a difference between the first and second values exceeds a predetermined amount, and
providing an output signal indicative of whether the difference exceeds the predetermined amount.
9. The method of claim 8 , further comprising:
coupling a second logic element to the first logic element; and
causing the second logic element to change state upon the state transition of the first logic element.
10. The method of claim 8 , wherein the first logic element is an exclusive NOR gate.
11. The method of claim 8 , wherein when the difference between the first and second values exceeds the predetermined amount, an anomaly at the inputs to the first logic element causes the first logic element to transition state.
12. The method of claim 8 , further comprising:
coupling a third logic element to the inputs of the first logic element; and
using the third logic element to determine a phase difference between the inputs to the first logic element.
13. The method of claim 12 , wherein the phase difference between the inputs to the first logic element is indicative of which of the at least first and second capacitances is larger.
14. An integrated circuit, comprising:
a plurality of circuit portions;
at least first and second parasitic capacitances associated with each of the plurality of circuit portions, the first and second parasitic capacitances having first and second capacitance values associated therewith;
means for providing a transient stimulus signal to the at least first and second parasitic capacitances;
a first logic element associated with each of the plurality of circuit portions and coupled to the transient stimulus signal providing means and to the at least first and second capacitances, the first logic element being configured to switch state: (a) upon detecting the stimulus signal, and (b) when a difference between the first and second values exceeds a predetermined amount, and
means, operably coupled to the first logic element, for providing an output signal indicative of whether the difference exceeds the predetermined amount.
15. The integrated circuit of claim 14 , further comprising:
a second logic element associated with each of the plurality of circuit portions and coupled to the first logic element, the second logic element being configured to change state upon the state transition of the first logic element.
16. The integrated circuit of claim 14 , wherein the first logic element is an exclusive NOR gate.
17. The integrated circuit of claim 14 , wherein when the difference between the first and second values exceeds the predetermined amount, an anomaly at the inputs to the first logic element causes the first logic element to transition state.
18. The integrated circuit of claim 14 , further comprising a third logic element associated with each of the plurality of circuit portions and coupled to the inputs of the first logic element, the third logic element being configured to determine a phase difference between the inputs to the first logic element.
19. The integrated circuit of claim 18 , wherein the phase difference between the inputs to the first logic element is indicative of which of the first and second capacitances is larger.
20. The integrated circuit of claim 14 , wherein the first and second parasitic capacitances are generated by data lines, circuit traces or circuit components.