Calibration circuit and semiconductor device incorporating the same
View Patent ↗Impedance adjusting transistors are once inactivated on every occasion of changing an impedance adjusting code. After restoring the potential to an initially set potential by once inactivating the impedance adjusting transistors, the state of the transistors is switched according to the impedance adjusting code. By starting the potential from the initially set potential at the time of switching the state of the transistors, no switching noise is generated. Since no switching noise is generated, a comparator always carries out stable comparison and judgment and thus there is obtained a calibration circuit that ensures stable outputs.
1. A calibration circuit comprising
a replica circuit connected to a calibration terminal,
a comparator which compares a potential at said calibration terminal and a reference potential,
a counter which performs a count operation in response to an output of said comparator, and
a control circuit which outputs an impedance control signal in response to a count output and a mask signal from said counter, said impedance control signal used for controlling an impedance of said replica circuit,
wherein said impedance control signal is set to an initial state to inactivate said replica circuit by said mask signal during a transition of said count output.
2. A calibration circuit according to claim 1 , wherein said replica circuit comprises a plurality of transistors connected in parallel with each other, and
wherein said impedance control signal is input to the gates of said plurality of transistors to control the on/off states of each of said plurality of resistors, thereby controlling the impedance of said replica circuit.
3. A calibration circuit according to claim 2 , wherein said replica circuit has substantially a same structure as a structure on a load side at a final stage of an output circuit and is interposed between said calibration terminal and a supply potential.
4. A calibration circuit according to claim 2 , wherein said replica circuit has substantially a same structure as a structure on a driver side at a final stage of an output circuit and is interposed between a circuit node having a same potential as said calibration terminal and a ground potential.
5. A calibration circuit according to claim 2 , wherein said counter asserts said mask signal to cause said impedance control signal to inactivate said plurality of transistors during a transition of said counter output.
6. A calibration circuit according to claim 5 , wherein said counter maintains said count output when said mask signal is de-asserted.
7. A calibration circuit according to claim 1 , wherein said replica circuit includes a pull-up circuit connected between a supply potential and said calibration terminal.
8. A calibration circuit according to claim 7 , further comprising
a second pull-up circuit receiving said impedance control signal,
a pull-down circuit,
a second comparator which compares a potential at a contact point between said second pull-up circuit and said pull-down circuit and the reference potential,
a second counter which performs a count operation in response to an output of said second comparator, and
a second control circuit which outputs a second impedance control signal in response to a second count output and a second mask signal from said second counter, said second impedance control signal used for controlling impedance of said pull-down circuit,
wherein said second impedance control signal is set to an initial state by said second mask signal when said second count output changes.
9. A calibration circuit according to claim 8 , wherein said second pull-up circuit has substantially a same structure as a structure on a load side at a final stage of an output circuit and is interposed between one end of said pull-down circuit and the supply potential.
10. A calibration circuit according to claim 8 , wherein said pull-down circuit has substantially a same structure as a structure on a driver side at a final stage of an output circuit and is interposed between one end of said second pull-up circuit and a ground potential.
11. A calibration circuit according to claim 7 , wherein said pull-up circuit has substantially a same structure as a structure on a load side at a final stage of an output circuit and is interposed between said calibration terminal and the supply potential.
12. A semiconductor device comprising a calibration circuit including:
a replica circuit connected to a calibration terminal,
a comparator which compares a potential at said calibration terminal and a reference potential,
a counter which performs a count operation in response to an output of said comparator, and
a control circuit which outputs an impedance control signal in response to a count output and a mask signal from said counter, said impedance control signal used for controlling impedance of said replica circuit,
wherein said impedance control signal is set to an initial state to inactivate said replica circuit by said mask signal during a transition of said count output.
13. A semiconductor device according to claim 12 , wherein said replica circuit comprises a plurality of transistors connected in parallel with each other, and
wherein said impedance control signal is input to the gates of said plurality of transistors to control the on/off states of each of said plurality of transistors, thereby controlling the impedance of said replica circuit.
14. A semiconductor device according to claim 13 , wherein said replica circuit has substantially a same structure as a structure on a load side at a final stage of an output circuit and is interposed between said calibration terminal and a supply potential.
15. A semiconductor device according to claim 13 , wherein said replica circuit has substantially a same structure as a structure on a driver side at a final stage of an output circuit and is interposed between a circuit node having a same potential as said calibration terminal and a ground potential.
16. A semiconductor device according to claim 13 , wherein said counter asserts said mask signal to cause said impedance control signal to inactivate said plurality of transistors during a transition of said counter output.
17. A semiconductor device according to claim 16 , wherein said counter maintains said count output when said mask signal is de-asserted.
18. A calibration circuit according to claim 12 , wherein said replica circuit includes a pull-up circuit connected between a supply potential and said calibration terminal.
19. A calibration circuit according to claim 18 , further comprising
a second pull-up circuit receiving said impedance control signal,
a pull-down circuit,
a second comparator which compares a potential at a contact point between said second pull-up circuit and said pull-down circuit and the reference potential,
a second counter which performs a count operation in response to an output of said second comparator, and
a second control circuit which outputs a second impedance control signal in response to a second count output and a second mask signal from said second counter, said second impedance control signal used for controlling impedance of said pull-down circuit,
wherein said second impedance control signal is set to an initial state by said second mask signal when said second count output changes.
20. A calibration circuit according to claim 19 , wherein said second pull-up circuit has substantially a same structure as a structure on a load side at a final stage of an output circuit and is interposed between one end of said pull-down circuit and the supply potential.
21. A calibration circuit according to claim 19 , wherein said pull-down circuit has substantially a same structure as a structure on a driver side at a final stage of an output circuit and is interposed between one end of said second pull-up circuit and a ground potential.
22. A calibration circuit according to claim 18 , wherein said pull-up circuit has substantially a same structure as a structure on a load side at a final stage of an output circuit and is interposed between said calibration terminal and the supply potential.
23. A calibration circuit comprising:
a replica circuit connected to a calibration terminal;
a comparator which compares a potential at said calibration terminal and a reference potential;
a counter which performs a count operation in response to an output of said comparator, produces a count output, and produces a mask signal during a transition of said count output; and
a control circuit which outputs an impedance control signal in response to said count output, said impedance control signal used for controlling impedance of said replica circuit, the control circuit further sets said impedance control signal to an initial state in response to said mask signal.
24. The calibration circuit according to claim 23 , wherein said replica circuit is inactivated by the initial state of the impedance control signal.