Use of a thick oxide device as a cascode for a thin oxide transconductance device in MOSFET technology and its application to a power amplifier design
View Patent ↗A power amplifier power amplifier includes a transconductance stage and a cascode stage. The transconductance stage that is operable to receive an input voltage signal and to produce an output current signal. The transconductance stage includes a first Metal Oxide Silicon (MOS) transistor having a first gate oxide thickness and a first channel length. The cascode stage communicatively couples to the transconductance stage and is operable to receive the output current signal and to produce an output voltage signal based thereupon. The cascode stage includes a second MOS transistor having a second gate oxide thickness and a second channel length.
1. An amplifier comprising:
a primary transconductance stage to receive a primary bias voltage to produce a primary current output;
a secondary transconductance stage to receive a secondary bias voltage to produce a secondary current output that combines with the primary current output;
wherein each of the primary and secondary transconductance stages includes a cascoded pair of transistors, in which a first transistor of the cascoded pair operates as a transconductance transistor and a second transistor of the cascoded pair operates as a cascode transistor, and in which the second transistor has a gate oxide thickness that is substantially thicker than a gate oxide thickness of the first transistor.
2. The amplifier of claim 1 , wherein the gate oxide thickness of the second transistor is approximately twice as thick as the gate oxide thickness of the first transistor.
3. The amplifier of claim 1 , wherein the gate oxide thickness of the second transistor is approximately 100 Angstroms and the gate oxide thickness of the first transistor is approximately 50 Angstroms.
4. The amplifier of claim 1 , wherein a channel length of the second transistor is substantially longer than a channel length of the first transistor.
5. The amplifier of claim 4 , wherein the channel length of the second transistor is approximately twice as long as the channel length of the first transistor.
6. The amplifier of claim 4 , wherein the channel length of the second transistor is approximately 0.35 microns and the channel length of the first transistor is approximately 0.18 microns.
7. The amplifier of claim 1 , further comprising a signal level detection and bias determination module to apply the primary and secondary bias voltages.
8. The amplifier of claim 1 , wherein the primary the secondary transconductance stages are differential stages with each stage having a respective differential pair of first and second transistors.
9. The amplifier of claim 1 , wherein the primary transconductance stage and the secondary transconductance stage are to be biased at different bias levels.