Method of forming integrated circuit devices having n-MOSFET and p-MOSFET transistors with elevated and silicided source/drain structures
View Patent ↗An n-FET and a p-FET each have elevated source/drain structures. Optionally, the p-FET elevated-SOURCE/DRAIN structure is epitaxially grown from a p-FET recess formed in the substrate. Optionally, the n-FET elevated-SOURCE/DRAIN structure is epitaxially grown from an n-FET recess formed in the substrate. The n-FET and p-FET elevated-source/drain structures are both silicided, even though the structures may have different materials and/or different structure heights. At least a thermal treatment portion of the source/drain structure siliciding is performed simultaneously for the n-FET and p-FET elevated source/drain structures. Also, the p-FET gate electrode, the n-FET gate electrode, or both, may optionally be silicided simultaneously (same metal and/or same thermal treatment step) with the n-FET and p-FET elevated-source/drain structures, respectively; even though the gate electrodes may have different materials, different silicide metal, and/or different electrode heights. The silicides formed on n-FET and p-FET elevated-source/drain structures preferably do not extend below a top surface of the substrate more than about 250 angstroms; and the structure heights may be selected to provide this.
1. A method of forming an integrated circuit device, comprising:
forming an n-FET gate dielectric on a substrate and a p-FET gate dielectric on the substrate;
forming an n-FET gate electrode on the n-FET gate dielectric and a p-FET gate electrode on the p-FET gate dielectric, wherein the n-FET gate electrode and the p-FET gate electrode each comprise metal, wherein the n-FET gate dielectric is located between the n-FET gate electrode and the substrate at an n-FET channel region, and the p-FET gate dielectric is located between the p-FET gate electrode and the substrate at a p-FET channel region;
forming an n-FET spacer structure adjacent to the n-FET gate electrode;
forming a p-FET spacer structure adjacent to the p-FET gate electrode;
forming an elevated n-FET source/drain structure adjacent to the n-FET gate electrode, such that the n-FET spacer structure is located at least partially between the elevated n-FET source/drain structure and the n-FET gate;
forming an elevated p-FET source/drain structure adjacent to the p-FET gate electrode, such that the p-FET spacer structure is located at least partially between the elevated p-FET source/drain structure and the p-FET gate electrode; and
siliciding at least a first portion of the elevated n-FET source/drain structure and at least a first portion of the elevated p-FET source/drain structure in a source/drain-structure silicidation step, wherein at least a thermal treatment portion of the source/drain structure siliciding is performed simultaneously for the elevated n-FET source/drain structure and for the elevated p-FET source/drain structure, wherein the at least a first portion of the elevated n-FET source/drain structure extends to at least the surface of the substrate.
2. The method of claim 1 , wherein the source/drain-structure silicidation step further comprises:
forming a protective mask;
depositing a metal layer over the n-FET and p-FET source/drain structures; and
applying a thermal treatment.
3. The method of claim 1 , wherein the n-FET gate electrode is also silicided during the source/drain-structure silicidation step.
4. The method of claim 1 , wherein the n-FET gate electrode is silicided in a gate-electrode silicidation step, wherein the source/drain-structure silicidation step is different from the gate-electrode silicidation step.
5. The method of claim 1 , wherein the p-FET gate electrode is also silicided during the source/drain-structure silicidation step.
6. The method of claim 1 , wherein the p-FET gate electrode is silicided in a gate-electrode silicidation step, wherein the source/drain-structure silicidation step is different from the gate-electrode silicidation step.
7. A method of forming an integrated circuit device, comprising:
forming an n-FET gate dielectric on a substrate and a p-FET gate dielectric on the substrate;
forming an n-FET gate electrode on the n-FET gate dielectric and a p-FET gate electrode on the p-FET gate dielectric, wherein the n-FET gate electrode and the p-FET gate electrode each comprise metal, wherein the n-FET gate dielectric is located between the n-FET gate electrode and the substrate at an n-FET channel region, and the p-FET gate dielectric is located between the p-FET gate electrode and the substrate at a p-FET channel region;
forming an n-FET spacer structure adjacent to the n-FET gate electrode;
forming a p-FET spacer structure adjacent to the p-FET gate electrode;
forming an elevated n-FET source/drain structure adjacent to the n-FET gate electrode, such that the n-FET spacer structure is located at least partially between the elevated n-FET source/drain structure and the n-FET gate electrode;
forming an elevated p-FET source/drain structure adjacent to the p-FET gate electrode, such that the p-FET spacer structure is located at least partially between the elevated p-FET source/drain structure and the p-FET gate electrode; and
siliciding at least a first portion of the elevated n-FET source/drain structure and at least a first portion of the elevated p-FET source/drain structure in a source/drain-structure silicidation step, wherein at least a thermal treatment portion of the source/drain structure siliciding is performed simultaneously for the elevated n-FET source/drain structure and for the elevated p-FET source/drain structure;
wherein the p-FET metal gate electrode is silicided in a p-FET gate-electrode silicidation step and the n-FET gate electrode is silicided in an n-FET gate-electrode silicidation step, wherein the source/drain-structure silicidation step is different from the p-FET gate-electrode silicidation step, the source/drain-structure silicidation step is different from the n-FET gate-electrode silicidation step, and the p-FET gate-electrode silicidation step is different from the n-FET gate-electrode silicidation step.
8. The method of claim 1 , wherein the p-FET gate electrode and the n-FET gate electrode are simultaneously silicided in a gate-electrode silicidation step, wherein the source/drain-structure silicidation step is different from the gate-electrode silicidation step.
9. The method of claim 1 , further comprising:
forming an n-FET recess in the substrate adjacent to the n-FET spacer structure; and
wherein the elevated n-FET source/drain structure extends from the substrate in the n-FET recess.
10. The method of claim 1 , further comprising:
selecting an n-FET source/drain structure height to control a depth of the silicidation of the n-FET source/drain structure so that the silicidation depth is not more than about 250 angstroms below a top surface of the substrate.
11. The method of claim 1 , further comprising:
forming an n-FET recess in the substrate adjacent to the n-FET spacer structure; and
epitaxially growing the elevated n-FET source/drain structure from the substrate in the n-FET recess, wherein the epitaxial growing is performed using a selective epitaxial growth process.
12. The method of claim 11 , wherein the elevated n-FET source/drain structure comprises Si:C, having about 1-2% carbon.
13. The method of claim 1 , wherein the forming of the elevated p-FET source/drain structure comprises epitaxially growing the elevated p-FET source/drain structure from a p-FET recess in the substrate, wherein the epitaxial growing is performed using a selective epitaxial growth process.
14. The method of claim 13 , wherein the elevated p-FET source/drain structure comprises SiGe.
15. The method of claim 1 , wherein the n-FET gate dielectric and the p-FET gate dielectric each comprise a same high-k dielectric material layer.
16. A method of forming an integrated circuit device, comprising:
forming an n-FET gate dielectric on a substrate and a p-FET gate dielectric on the substrate, wherein the n-FET gate dielectric and the p-FET gate dielectric each comprise high-k dielectric material;
forming an n-FET gate electrode structure on the n-FET gate dielectric and a p-FET gate electrode structure on the p-FET gate dielectric, wherein the n-FET gate dielectric is located between the n-FET gate electrode structure and the substrate at an n-FET channel region, and the p-FET gate dielectric is located between the p-FET gate electrode structure and the substrate at a p-FET channel region;
forming an n-FET spacer structure adjacent to the n-FET gate electrode;
forming an n-FET recess in the substrate adjacent to the n-FET spacer structure after forming the n-FET spacer structure;
epitaxially growing an elevated n-FET source/drain structure from the substrate in the n-FET recess, wherein the epitaxial growing is performed using a first selective epitaxial growth process, such that the n-FET spacer structure is located at least partially between the elevated n-FET source/drain structure and the n-FET gate electrode;
forming a p-FET spacer structure adjacent to the p-FET gate electrode;
forming a p-FET recess in the substrate adjacent to the p-FET spacer structure;
epitaxially growing an elevated p-FET source/drain structure from the substrate in the p-FET recess, wherein the epitaxial growing is performed using a first selective epitaxial growth process, such that the p-FET spacer structure is located at least partially between the elevated p-FET source/drain structure and the p-FET gate electrode; and
simultaneously siliciding the elevated n-FET source/drain structure and the elevated p-FET source/drain structure.
17. The method of claim 16 , further comprising:
simultaneously siliciding the p-FET gate electrode structure, n-FET gate electrode structure, or both, while siliciding the elevated n-FET source/drain structure and the elevated p-FET source/drain structure.
18. The method of claim 17 , further comprising:
selecting an n-FET source/drain structure height to control a silicidation depth of the n-FET source/drain structure so that the silicidation depth of the n-FET source/drain structure is not more than about 250 angstroms below a top surface of the substrate; and
selecting an p-FET source/drain structure height to control a silicidation depth of the p-FET source/drain structure so that the silicidation depth of the p-FET source/drain structure is not more than about 250 angstroms below the top surface of the substrate.
19. A method of forming an integrated circuit device, comprising:
forming an n-FET gate dielectric on a substrate and a p-FET gate dielectric on the substrate, wherein the n-FET gate dielectric and the p-FET gate dielectric each comprise high-k dielectric material;
forming an n-FET gate electrode structure on the n-FET gate dielectric and a p-FET gate electrode structure on the p-FET gate dielectric, wherein the n-FET gate dielectric is located between the n-FET gate electrode structure and the substrate at an n-FET channel region, and the p-FET gate dielectric is located between the p-FET gate electrode structure and the substrate at a p-FET channel region;
forming an n-FET spacer structure adjacent to the n-FET gate electrode;
forming a p-FET spacer structure adjacent to the p-FET gate electrode;
forming an elevated n-FET source/drain structure adjacent to the n-FET gate electrode, such that the n-FET spacer structure is located at least partially between the elevated n-FET source/drain structure and the n-FET gate electrode;
forming a p-FET recess in the substrate adjacent to the p-FET spacer structure;
forming an elevated p-FET source/drain structure extending from the substrate in the p-FET recess, such that the p-FET spacer structure is located at least partially between the elevated p-FET source/drain structure and the p-FET gate electrode; and
simultaneously siliciding the elevated n-FET source/drain structure and the elevated p-FET source/drain structure;
also simultaneously siliciding the p-FET gate electrode structure, n-FET gate electrode structure, or both, while siliciding the elevated n-FET source/drain structure and the elevated p-FET source/drain structure;
selecting an n-FET source/drain structure height to control a silicidation depth of the n-FET source/drain structure so that the silicidation depth of the n-FET source/drain structure is not more than about 250 angstroms below a top surface of the substrate; and
selecting a p-FET source/drain structure height to control a silicidation depth of the p-FET source/drain structure so that the silicidation depth of the p-FET source/drain structure is not more than about 250 angstroms below the top surface of the substrate.
20. The method of claim 19 , further comprises forming an n-FET recess in the substrate adjacent to the n-FET spacer structure; and
wherein the forming of the elevated n-FET source/drain structure comprises epitaxially growing an elevated n-FET source/drain structure from the substrate in the n-FET recess, wherein the epitaxial growing is performed using a first selective epitaxial growth process.