Patent Assignment
Reel/Frame 064180/0278
Assignment of Assignor's Interest
Recorded: 2023-06-30
Pages: 8
Assignor
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
Executed: 2023-06-20
Assignee
ADVANCED MANUFACTURING INNOVATIONS INC.
251 LITTLE FALLS DRIVE, WILMINGTON, DELAWARE, 19808
Covered Properties
(62)
Method for Forming Dielectric Film to Improve Adhesion of Low-K Film
Integrated Circuit Having Improved Interconnect Structure
Fin-Fet Device Structure Formed Employing Bulk Semiconductor Substrate
Interconnection Structure Design for Low Rc Delay and Leakage
Method of Making a Deep Junction for Electrical Crosstalk Reduction of an Image Sensor
Method of Forming Integrated Circuit Devices Having N-Mosfet and P-Mosfet Transistors with Elevated and Silicided Source/Drain Structures
Guard Ring Structure for Improving Crosstalk of Backside Illuminated Image Sensor
Three-Dimensional Integrated Circuits with Protection Layers
Multi-Die Wafer Level Packaging
Low-Cost and Ultra-Fine Integrated Circuit Packaging Technique
Enhanced Copper Posts for Wafer Level Chip Scale Packaging
Integrated Circuit Structures with Multiple Finfets
System and Method for Source/Drain Contact Processing
Integrating a First Contact Structure in a Gate Last Process
Multi-Die Wafer Level Packaging
Selective Etch-Back Process for Semiconductor Devices
Integrated Circuits Including Air Gaps Around Interconnect Structures, and Fabrication Methods Thereof
Integrated Circuit Including a Gate and a Metallic Connecting Line
Layout for Multiple-Fin Sram Cell
Wafer Backside Interconnect Structure Connected to Tsvs
Integrating a First Contact Structure in a Gate Last Process
Finfets with Multiple Fin Heights
Three-Dimensional Integrated Circuits with Protection Layers
Enhanced Copper Posts for Wafer Level Chip Scale Packaging
Multi-Fin Device by Self-Aligned Castle Fin Formation
System and Method for Source/Drain Contact Processing
Three-Dimensional Integrated Circuits with Protection Layers
Integrating a First Contact Structure in a Gate Last Process
System and Method for Source/Drain Contact Processing
Three-Dimensional Integrated Circuits with Protection Layers
3D-Stacked Backside Illuminated Image Sensor and Method of Making the Same
Multi-Fin Device by Self-Aligned Castle Fin Formation
Finfets with Multiple Fin Heights
Integrating a First Contact Structure in a Gate Last Process
Layout for Multiple-Fin Sram Cell
Integrated Circuits Including Air Gaps Around Interconnect Structures, and Fabrication Methods Thereof
Finfets with Multiple Fin Heights
Structure and Method for 3D Image Sensor
Methods of Forming Integrated Circuits
Finfets with Different Fin Height and Epi Height Setting
Method of Forming Semiconductor Structure with Horizontal Gate All Around Structure
Wafer Backside Interconnect Structure Connected to Tsvs
Wafer Backside Interconnect Structure Connected to Tsvs
Methods of Making Integrated Circuits Including Air Gaps Around Interconnect Structures
Semiconductor Devices with Horizontal Gate All Around Structure and Methods of Forming the Same
Method of Forming Horizontal Gate All Around Structure
Structure and Method for 3D Image Sensor
FinFETs with Different Fin Height and EPI Height Setting
FinFETs with Different Fin Height and EPI Height Setting
Layout for Multiple-Fin Sram Cell
Patent:
47,409 →
Application:
15/041,843 →
Method of Forming Horizontal Gate All Around Structure
Wafer Backside Interconnect Structure Connected to TSVs
Structure and Method for 3D Image Sensor
Structure and Method for 3D Image Sensor
Layout for Multiple-Fin SRAM Cell
Patent:
49,203 →
Application:
16/422,627 →
Structure and Method for 3D Image Sensor
Integrating a First Contact Structure in a Gate Last Process
Application:
61/091,933 →
Selective Etch-Back Process for Semiconductor Devices
Application:
61/147,164 →
Integrated Circuits Including Ild Structure, Systems, and Fabrication Methods Thereof
Application:
61/176,002 →
Wafer Backside Interconnect Structure Connected to TSVs
Application:
61/244,773 →
FinFETs with Multiple Fin Heights
Application:
61/266,427 →
3D CMOS Imaging Sensor
Application:
61/799,113 →
Related Assignments
(16)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Apr 24, 2006
From: TSAI, FANG WEN; CHEN, I-I; WU, ZHEN-CHENG; LIN, CHIH-LUNG
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 017852/0326 →
Assignment of Assignor's Interest
May 27, 2006
From: CHEN, KUANG-HSIN; LU, JHI-CHERNG; HSU, PENG-GU; LEE, DI-HONG
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 017942/0685 →
Assignment of Assignor's Interest
Jun 1, 2006
From: YU, CHEN-HUA; YEH, MING-SHIH
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 017966/0918 →
Assignment of Assignor's Interest
Aug 11, 2006
From: YAO, CHIH-HSIANG; HUANG, TAI-CHUN; LIANG, MONG-SONG
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 018094/0807 →
Assignment of Assignor's Interest
Aug 31, 2006
From: CHANG, SHANG-YI; WANG, CHUNG; WUU, SHOU-GWO; YAUNG, DUN-NIAN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 018196/0391 →
Assignment of Assignor's Interest
Nov 8, 2006
From: LIM, PENG-SOON; HOU, YONG-TIAN; YING, JIN; TAO, HUN-JAN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 018497/0523 →
Assignment of Assignor's Interest
Jan 24, 2007
From: HSU, TZU-HSUAN; WUU, SHOU-GWO; YAUNG, DUN-NIAN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 018800/0219 →
Assignment of Assignor's Interest
Feb 5, 2007
From: YU, CHEN-HUA; CHIOU, WN-CHIH; WU, WENG-JIN; TU, HUNG-JUNG
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 018853/0632 →
Assignment of Assignor's Interest
May 31, 2007
From: CHEN, CHEN-SHIEN; CHING, KAI-MING; CHEN, CHIH-HUA; KUO, CHEN-CHENG
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 019363/0178 →
Assignment of Assignor's Interest
Jun 6, 2007
From: CHAO, CLINTON
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 019392/0066 →
Assignment of Assignor's Interest
Jul 17, 2007
From: CHANG, KUO-CHIN; PU, HAN-PING; TSAO, PEI-HAW
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 019568/0742 →
Assignment of Assignor's Interest
Aug 24, 2007
From: LEE, TSUNG-LIN; CHANG, CHANG-YUN; LIU, SHENG-DA; YANG, FU-LIANG
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 019745/0367 →
Assignment of Assignor's Interest
Oct 18, 2007
From: YU, CHEN-HUA; CHANG, CHENG-HUNG; YEH, CHEN-NAN; HSU, YU-RUNG
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 019979/0876 →
Assignment of Assignor's Interest
Jan 26, 2009
From: YEH, CHIUNG-HAN; WU, MING-YUAN; THEI, KONG-BENG; CHUANG, HARRY
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
Reel/Frame 022153/0747 →
Assignment of Assignor's Interest
Nov 13, 2009
From: CHEN, NENG-KUO; TZENG, KUO-HWA; TSAI, CHENG-YUAN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 023513/0395 →
Assignment of Assignor's Interest
Jun 7, 2010
From: CHEN, CHII-PING; CHEN, CHIH-HAO
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 024493/0115 →