Wafer backside interconnect structure connected to TSVs
View Patent ↗An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line.
1. An integrated circuit structure comprising:
a semiconductor substrate having an active semiconductor device formed on a first side of the semiconductor substrate;
a conductive via passing through the semiconductor substrate;
a metal feature on a second side of the semiconductor substrate opposing the first side of the semiconductor substrate, the metal feature comprising:
a metal pad overlying and contacting the conductive via, wherein from a top-down perspective, all horizontal dimensions of the metal pad are greater than respective horizontal dimensions of the conductive via; and
a metal line higher than the conductive via, relative the second side of the semiconductor substrate, wherein the metal line comprises a dual damascene structure; and
a bump overlying the metal line.
2. The integrated circuit structure of claim 1 , wherein the metal pad further comprises:
a first bottom surface contacting a conductive barrier layer, wherein the conductive barrier layer contacts a top surface of the conductive via; and
a second bottom surface higher than the second side of the semiconductor substrate and lower than the first bottom surface.
3. The integrated circuit structure of claim 1 , wherein the dual damascene structure is in a same dielectric layer as the metal pad.
4. The integrated circuit structure of claim 1 , wherein the dual damascene structure is in a dielectric layer over the metal pad.
5. The integrated circuit structure of claim 1 further comprising a polyimide layer, wherein the metal pad is in the polyimide layer.
6. The integrated circuit structure of claim 1 , wherein the metal feature further comprises a conductive barrier layer.
7. An integrated circuit structure comprising:
a semiconductor substrate having a front side and a backside, wherein the backside is opposite the front side;
an active device formed on the front side;
a through-substrate via (TSV) penetrating through the semiconductor substrate;
a first dielectric layer on the backside of the semiconductor substrate, wherein the dielectric layer comprises a metal pad overlying the TSV, wherein from a top-down perspective, all horizontal dimensions of the metal pad are greater than respective horizontal dimensions of the TSV; and
a second dielectric layer on the backside of the semiconductor substrate and over the first dielectric layer relative the backside of the semiconductor substrate, the second dielectric layer comprises a first metal line, wherein the first metal line comprises a dual-damascene structure.
8. The integrated circuit structure of claim 7 , wherein the metal pad comprises a conductive barrier layer.
9. The integrated circuit structure of claim 7 , wherein the first metal line further comprises a conductive barrier layer.
10. The integrated circuit structure of claim 7 , wherein the second dielectric layer further comprises a second metal line, the second metal line comprising a single damascene structure.
11. The integrated circuit structure of claim 7 , wherein the TSV comprises a portion penetrating into the first dielectric layer.
12. The integrated circuit structure of claim 7 , further comprising an isolation layer covering at least a portion of sidewalls of the TSV.
13. The integrated circuit structure of claim 7 , wherein the first dielectric layer comprises a portion between the metal pad and the semiconductor substrate.
14. The integrated circuit structure of claim 7 , further comprising a bump overlying the first metal line.
15. The integrated circuit structure of claim 7 , wherein the metal pad comprises:
a first bottom surface contacting a top surface of the TSV; and
a second bottom surface higher than the backside of the semiconductor substrate and lower than the first bottom surface.
16. An integrated circuit structure comprising:
a semiconductor substrate having a front side and a backside, wherein the backside is opposite the front side;
an active device formed on the front side;
a through-substrate via (TSV) penetrating through the semiconductor substrate; and
a dielectric layer on the backside of the semiconductor substrate, wherein the dielectric layer comprises:
a metal pad overlying the TSV, wherein from a top-down perspective, all horizontal dimensions of the metal pad are greater than respective horizontal dimensions of the TSV; and
a metal line, wherein the metal line comprises a dual-damascene structure.
17. The integrated circuit structure of claim 14 , wherein the metal pad and the metal line comprise a conductive barrier layer, respectively.
18. The integrated circuit structure of claim 14 , further comprising a bump overlying the metal line.
19. The integrated circuit structure of claim 16 , wherein the metal pad comprises:
a first bottom surface contacting a top surface of the TSV; and
a second bottom surface higher than the backside of the semiconductor substrate and lower than the first bottom surface.