Multi-fin device by self-aligned castle fin formation
View Patent ↗The present disclosure provides a method includes forming a multi-fin device. The method includes forming a patterned mask layer on a semiconductor substrate. The patterned mask layer includes a first opening having a first width W 1 and a second opening having a second width W 2 less than the first width. The patterned mask layer defines a multi-fin device region and an inter-device region, wherein the inter-device region is aligned with the first opening; and the multi-fin device region includes at least one intra-device region being aligned with the second opening. The method further includes forming a material layer on the semiconductor substrate and the patterned mask layer, wherein the material layer substantially fills in the second opening; performing a first etching process self-aligned to remove the material layer within the first opening such that the semiconductor substrate within the first opening is exposed; performing a second etching process to etch the semiconductor substrate within the first opening, forming a first trench in the inter-device region; and thereafter performing a third etching process to remove the material layer in the second opening.
1. A multi-fin device, comprising:
a multi-fin transistor formed on a semiconductor substrate, wherein the multi-fin transistor includes a first fin active region and a second fin active region;
an inter-device isolation feature formed in the semiconductor substrate, adjacent the multi-fin transistor, and having a first width W 1 and a first depth D 1 ; and
an intra-device isolation feature formed in the semiconductor substrate and extending continuously from the first fin active region to the second fin active region, wherein the entire intra-device isolation feature has a second width W 2 different from W 1 and a second depth D 2 different from D 1 , wherein the first depth D 1 is at least two times greater than the second depth D 2 .
2. The multi-fin device of claim 1 , wherein the first depth D 1 ranges between about 1600 angstrom and about 2000 angstrom and the second depth D 2 ranges between about 400 angstrom and about 800 angstrom.
3. The multi-fin device of claim 1 , wherein the first width W 1 is greater than about 200 nm and the second width W 2 ranges between about 10 nm and about 30 nm.
4. The multi-fin device of claim 1 , wherein the multi-fin transistor further includes a third fin active region, wherein the second fin active region is disposed between the first fin active region and the third fin active region.
5. The multi-fin device of claim 4 , further comprising another intra-device isolation feature formed in the semiconductor substrate and disposed between the second fin active region and the third fin active region, and
wherein the intra-device isolation feature is disposed between the first in active region and the second fin active region.
6. The multi-fin device of claim 5 , wherein the another intra-device isolation feature has the second width W 2 and the second depth D 2 .
7. The multi-fin device of claim 1 , further comprising another inter-device isolation feature formed in the semiconductor substrate adjacent the multi-fin transistor.
8. The multi-fin device of claim 7 , wherein the another inter-device isolation features is adjacent a first side of the multi-fin transistor and the inter-device isolation features is adjacent a second side of the multi-fin transistor, the first side of the multi-fin transistor being opposed by the second side of the multi-fin transistor.
9. A device comprising:
a multi-fin transistor formed on a semiconductor substrate, wherein the multi-fin transistor includes a first fin active region and a second fin active region;
a first isolation region formed in the semiconductor substrate on a first side of the multi-fin transistor, the first isolation region having a first depth D 1 ;
a second isolation region formed in the semiconductor substrate on a second side of the multi-fin transistor, the second isolation region having the first depth D 1 ; and
a third isolation region formed in the semiconductor substrate and extending continuously from the first fin active region to the second fin active region, the entire third isolation region having a second depth D 2 that is different than the first depth D 1 , wherein the first depth D 1 is at least two times greater than the second depth D 2 .
10. The device of claim 9 , wherein the first isolation region has a first width W 1 and the third isolation region has a second width W 2 extending from a side of the first fin active region to the second fin active region, wherein the first width W 1 is greater than the second width W 2 .
11. The device of claim 9 , further comprising a fourth isolation region formed in the semiconductor substrate proximate the second fin active region, the fourth isolation region having the second depth D 2 .
12. The device of claim 11 , wherein the multi-fin transistor further includes a third fin active region and the fourth isolation region is disposed between the second fin active region and the third fin active region.
13. The device of claim 12 , wherein a first width of the third isolation region extending form a side of the first fin active region to a side of the second fin active region is equal to a second width of the fourth isolation region extending from another side of the second fin active region to a side of the third fin active region.
14. A device comprising:
a transistor formed on a front side of a semiconductor substrate, the transistor having a first fin active region and a second fin active region;
a first isolation region formed in the semiconductor substrate on a first side of the multi-fin transistor, the first isolation region having a first depth D 1 and a first width W 1 , wherein the semiconductor substrate has a first thickness that extends from the first isolation region at the first depth to a back side of the semiconductor substrate, wherein the back side of the semiconductor substrate is opposite the front side of the semiconductor substrate; and
a second isolation region formed in the semiconductor substrate between the first and second fin active regions, the second isolation region having a second depth D 2 that is different than the first depth D 1 and a second width W 2 that is different than the first width W 2 , wherein the first depth D 1 is at least two times greater than the second depth D 2 , wherein the semiconductor substrate has a second thickness that extends from the second isolation region at the second depth to the back side of the semiconductor substrate, wherein the second thickness of the semiconductor substrate is greater than the first thickness of the semiconductor substrate.
15. The device of claim 14 , wherein the first width W 1 is greater than the second width W 2 .
16. The device of claim 14 , further comprising a third isolation region formed in the semiconductor substrate proximate the second fin active region, the third isolation region having the second width W 2 and second depth D 2 .
17. The device of claim 16 , wherein the transistor further includes a third fin active region, and
wherein the third isolation region is disposed between the second fin active region and the third fin active region.
18. The device of claim 14 , further comprising a third isolation region formed in the semiconductor substrate on a second side of the transistor, the third isolation region having the first depth D 1 and the first width W 1 .
19. The device of claim 14 , wherein the second isolation region extends continuously from the first fin active region to the second fin active region, the entire second isolation region having the second depth D 2 that is different than the first depth D 1 and the second width W 2 that is different than the first width W 2 .
20. The device of claim 14 , wherein the first depth D 1 is about four times greater than the second depth D 2 .