IP Library Granted Patent US 9,159,808
Granted Patent B2
US 9,159,808 · App. 12/617,463 · Granted Oct 13, 2015

Selective etch-back process for semiconductor devices

Inventors: Neng-Kuo Chen (Sinshih Township, TW); Kuo-Hwa Tzeng (Taipei, TW); Cheng-Yuan Tsai (Chu-Pei, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L29/66795H01L21/31116H01L21/76232H01L29/7854
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Quick Facts
Patent No.
US 9,159,808
App. No.
12/617,463
Granted
Oct 13, 2015
Kind
B2
Abstract

A semiconductor device having fins and a method of manufacture are provided. A patterned mask is formed over a substrate. Trenches are formed in the substrate and the trenches are filled with a dielectric material. Thereafter, the patterned mask is removed and one or more etch processes are performed to recess the dielectric material, wherein at least one of the etch processes is an etch process that removes or prevents fences from being formed along sidewalls of the trench. The etch process may be, for example, a plasma etch process using NH 3 and NF 3 , an etch process using a polymer-rich gas, or an H 2 etch process.

Claims (34)

1. A method of forming a semiconductor device, the method comprising:

providing a substrate;

forming one or more fins in the substrate, wherein the fins are finFET fins;

completely filling an area between adjacent ones of the fins with a dielectric material, the filling comprising forming the dielectric material using a first method and a second method different from the first method, the dielectric material being the same material throughout the dielectric material; and

recessing the dielectric material below a top surface of the fins, at least a portion of the dielectric material along sidewalls of the fin above a bottom of a recess being substantially removed, thereby exposing at least a portion of the sidewalls of the fins, wherein the recessing comprises performing a first etch to recess the dielectric material such that fences of the dielectric material remain along the sidewalls of the fins and a second etch to remove the fences, the fences comprising a first portion along the sidewalls with a first width and a second portion along the sidewalls with a second width different from the first width.

2. The method of claim 1 , wherein the second etch comprises a plasma etch process using NH 3 and NF 3 .

3. The method of claim 1 , wherein the second etch comprises an etch process using a polymer-rich gas.

4. The method of claim 3 , wherein the polymer-rich gas comprises CHF 3 , CH 2 F 2 , CH 3 F, C 4 F 6 , C 4 F 8 , or C 5 F 8 .

5. The method of claim 1 , wherein the second etch comprises an H 2 etch process.

6. The method of claim 1 , wherein the recessing comprises performing a single etch.

7. The method of claim 6 , wherein the single etch comprises a plasma etch process using NH 3 and NF 3 .

8. The method of claim 6 , wherein the single etch comprises a process using a polymer-rich gas.

9. The method of claim 6 , wherein the single etch comprises an H 2 etch process.

10. A method of forming a semiconductor device, the method comprising:

providing a substrate;

forming one or more trenches in the substrate, wherein sidewalls of the one or more trenches are only semiconductor material;

completely filling at least one of the one or more trenches with a dielectric material of a single composition type, the dielectric material having a bottom surface extending across the at least one of the one or more trenches;

recessing the dielectric material within the one or more trenches, the recessing leaving fences of the dielectric material along the sidewalls of the one or more trenches while leaving the bottom surface; and

removing the fences of the dielectric material along the sidewalls of the one or more trenches such that at least portions of the sidewalls of the one or more trenches are exposed, the removing the fences leaving a portion of the dielectric material within each of the one or more trenches, wherein the portion of the dielectric material left has the bottom surface extending across at least one of the one or more trenches.

11. The method of claim 10 , wherein the removing the fences is performed at least in part by a plasma etch process using NH 3 and NF 3 .

12. The method of claim 10 , wherein the removing the fences is performed at least in part by an etch process using a polymer-rich gas.

13. The method of claim 12 , wherein the polymer-rich gas comprises CHF 3 , CH 2 F 2 , CH 3 F, C 4 F 6 , C 4 F 8 , or C 5 F 8 .

14. The method of claim 10 , wherein the removing the fences is performed at least in part by an H 2 etch process.

15. The method of claim 10 , wherein the removing results in a solid formed along a top surface of the dielectric material and further comprises removing the solid by sublimation.

16. A method of forming a semiconductor device, the method comprising:

providing a substrate having a trench formed therein;

filling all of the trench with a dielectric material;

planarizing the dielectric material;

performing a first etching process to recess the dielectric material such that a top surface of the dielectric material is below a top surface of the substrate, the first etching process leaving tapered fences of the dielectric material along sidewalls of the trench, wherein the sidewalls of the trench are only semiconductor material; and

performing a second etching process to remove the tapered fences thereby exposing portions of the sidewalls of the trench, wherein after the performing the second etching process the dielectric material extends from a first side of the trench to a second side of the trench.

17. The method of claim 16 , wherein the first etching process and the second etching process are a single continuous etch process.

18. The method of claim 16 , wherein the second etching process is a deposition-etch process.

19. The method of claim 16 , wherein the second etching process comprises a plasma etch process using NH 3 and NF 3 , an etch process using a polymer-rich gas, or an H 2 etch process.

20. The method of claim 16 , wherein the sidewalls of the trench are part of a finFET.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2023
From: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
To: ADVANCED MANUFACTURING INNOVATIONS INC.
Reel/Frame 064180/0278 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 13, 2009
From: CHEN, NENG-KUO; TZENG, KUO-HWA; TSAI, CHENG-YUAN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 023513/0395 →
Continuity (2)
Provisional Application 61147164 · Jan 26, 2009
Related Publication 20100190345A1 · Jul 29, 2010