FIN-FET device structure formed employing bulk semiconductor substrate
View Patent ↗A fin-FET device and a method for fabrication thereof both employ a bulk semiconductor substrate. A fin and an adjoining trough are formed within the bulk semiconductor substrate. The trough is partially backfilled with a deposited dielectric layer to form an exposed fin region and an unexposed fin region. A gate dielectric layer is formed upon the exposed fin region and a gate electrode is formed upon the gate dielectric layer. By employing a bulk semiconductor substrate the fin-FET device is fabricated cost effectively.
1. A fin-FET structure comprising:
a bulk semiconductor substrate having a fin and an adjoining trough wherein said fin consists of a single width;
a first dielectric layer filling the trough to a first height, said first dielectric layer being a substantially planar layer directly contacting the fin to provide an exposed fin region above said first height and an unexposed fin region below said first height;
a second dielectric layer over the first dielectric layer such as to define an aperture, said aperture comprising a apace extending horizontally between the second dielectric layer and a sidewall of the exposed fin region;
a gate dielectric layer upon the exposed fin region extending to said first dielectric layer and partially filling the aperture, said gate dielectric layer not upon said unexposed fin region; and
a gate electrode upon the gate dielectric layer and completely filling the aperture.
2. The fin-FET structure of claim 1 wherein the bulk semiconductor substrate is a bulk silicon semiconductor substrate.
3. The fin-FET structure of claim 1 wherein the fin has a height of from about 100 to about 10000 angstroms.
4. The fin-FET structure of claim 1 wherein the exposed fin region has a height of from about 50 to about 6000 angstroms and the unexposed fin region has a height of from about 50 to about 6000 angstroms.
5. The fin-FET structure of claim 1 further comprising a stop layer interposed between the first dielectric layer and the second dielectric layer, said space extending horizontally between said sidewall of the exposed fin region and the stop layer.
6. The fin-FET structure of claim 5 wherein the stop layer has a thickness of from about 100 to about 1000 angstroms.
7. The fin-FET structure of claim 5 wherein the stop layer comprises a silicon nitride material and each of the first dielectric layer and the second dielectric layer comprises a silicon oxide material.
8. A fin-FET structure comprising:
a bulk semiconductor substrate having a fin and an adjoining trough wherein said fin consists of a single width;
a first dielectric layer filling the trough to a first height and contacting the fin to provide an exposed fin region above said first height and an unexposed fin region below said first height;
a second dielectric layer over the first dielectric layer such as to define an aperture, said aperture comprising a space extending horizontally between the second dielectric layer and a sidewall of the exposed fin region;
a stop layer interposed between the first dielectric layer and the second dielectric layer, said space extending horizontally between said sidewall of the exposed fin region and the stop layer;
a gate dielectric layer upon the exposed fin region extending to said first dielectric layer, said gate dielectric layer not upon the unexposed fin region; and
a gate electrode upon the gate dielectric layer and completely filling the aperture.
9. The fin-FET structure of claim 8 wherein the bulk semiconductor substrate is a bulk silicon semiconductor substrate.
10. The fin-FET structure of claim 8 wherein the fin has a height of from about 100 to about 10000 angstroms.
11. The fin-FET structure of claim 8 wherein the exposed fin region has a height of from about 50 to about 6000 angstroms and the unexposed fin region has a height of from about 50 to about 6000 angstroms.
12. The fin-FET structure of claim 8 wherein the stop layer has a thickness of from about 100 to about 1000 angstroms.
13. The fin-FET structure of claim 8 wherein the stop layer comprises a silicon nitride material and each of the first dielectric layer and the second dielectric layer comprises a silicon oxide material.
14. A fin-FET structure comprising:
a bulk semiconductor substrate having a fin and an adjoining trough wherein said fin consists of a single width;
said fin has a height of from about 100 to about 10,000 angstroms;
a first dielectric layer filling the trough to a first height, said first dielectric layer is a substantially planar layer directly contacting the fin to provide an exposed fin region above said first height and an unexposed fin region below said first height;
a second dielectric layer over the first dielectric layer such as to define an aperture, said aperture comprising a space extending horizontally between the second dielectric layer and a sidewall of the exposed fin region;
a gate dielectric layer upon the exposed fin region extending to said first dielectric layer, said gate dielectric layer partially filling the aperture, said gate dielectric layer not upon said unexposed fin region; and
a gate electrode upon the gate dielectric layer and completely filling the aperture.
15. The fin-FET structure of claim 14 wherein the bulk semiconductor substrate is a bulk silicon semiconductor substrate.
16. The fin-FET structure of claim 14 further comprising a stop layer interposed between the first dielectric layer and the second dielectric layer, said space extending horizontally between said sidewall of the exposed fin region and the stop layer.
17. The fin-FET structure of claim 16 wherein the stop layer has a thickness of from about 100 to about 1000 angstroms.