IP Library Granted Patent US 8,394,692
Granted Patent B2
US 8,394,692 · App. 13/286,276 · Granted Mar 12, 2013

Integrating a first contact structure in a gate last process

Inventors: Chiung-Han Yeh (Tainan, TW); Ming-Yuan Wu (Hsinchu, TW); Kong-Beng Thei (Pao-Shan Village, TW); Harry Chuang (Hsinchu, TW); Mong-Song Liang (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,394,692
App. No.
13/286,276
Granted
Mar 12, 2013
Kind
B2
Abstract

A method is provided that includes providing a substrate; forming a transistor in the substrate, the transistor having a dummy gate; forming a dielectric layer over the substrate and transistor; forming a contact feature in the dielectric layer; and after forming the contact feature, replacing the dummy gate of the transistor with a metal gate. An exemplary contact feature is a dual contact.

Claims (19)

1. A method comprising:

providing a semiconductor substrate;

forming a transistor that includes a gate structure disposed over the semiconductor substrate, a source feature, and a drain feature, wherein the gate structure interposes the source feature and the drain feature and the gate structure includes a dummy gate;

forming a first dielectric layer over the semiconductor substrate and the transistor;

forming a first contact feature having a first width in the first dielectric layer, wherein the first contact feature is coupled to one of the source feature and the drain feature;

removing a portion of the first dielectric layer such that the dummy gate of the gate structure is exposed and a portion of the first dielectric layer remains;

replacing the dummy gate of the gate structure with a metal gate;

after replacing the dummy gate, forming a second dielectric layer over the remaining portion of the first dielectric layer; and

forming a second contact feature having a second width in the second dielectric layer, the second width being substantially the same as the first width, wherein the second contact feature is coupled to the first contact feature.

2. The method of claim 1 wherein the removing the portion of the first dielectric layer includes performing a chemical mechanical polishing on the first dielectric layer.

3. The method of claim 1 wherein the forming the second contact feature includes forming a contact plug having a metal barrier layer on sidewalls and a bottom of the contact plug, wherein the metal barrier layer effects coupling between the first contact feature and the second contact feature.

4. The method of claim 1 further including forming a metal interconnect layer over the second contact feature, wherein the metal interconnect layer is coupled to the second contact feature.

5. The method of claim 1 wherein the replacing the dummy gate of the gate structure with the metal gate includes:

performing an etch back process to remove the dummy gate from the gate structure, thereby forming a trench; and

forming a work function metal layer and a filler metal layer in the trench, thereby forming the metal gate.

6. The method of claim 1 further including forming a first dummy contact feature in the first dielectric layer when forming the first contact feature, wherein the first dummy contact feature is coupled to the semiconductor substrate.

7. The method of claim 6 further including forming a second dummy contact feature in the second dielectric layer when forming the second contact feature, wherein the second dummy contact feature is coupled to the first dummy contact feature.

8. The method of claim 7 wherein the first dummy contact feature and the second dummy contact feature have a substantially same width.

9. The method of claim 7 wherein a pattern density of a region of the semiconductor substrate where the first contact feature and the second contact feature is formed is substantially less than a pattern density of another region of the semiconductor substrate where the first dummy contact feature and the second dummy contact feature is formed.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2023
From: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
To: ADVANCED MANUFACTURING INNOVATIONS INC.
Reel/Frame 064180/0278 →
Continuity (4)
Division 12839994 · Jul 20, 2010
Division 12341891 · Dec 22, 2008
Provisional Application 61091933 · Aug 26, 2008
Related Publication 20120045889A1 · Feb 23, 2012