System and method for source/drain contact processing
View Patent ↗System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin.
1. A method for forming a semiconductor device, the method comprising:
forming a non-planar transistor on a substrate, the non-planar transistor comprising a fin with source/drain regions formed therein, the fin comprising a top surface and sidewalls;
forming an inter-layer dielectric over the non-planar transistor, the inter-layer dielectric having a maximum height;
forming an opening only partially through the maximum height of the inter-layer dielectric so as to expose at least a portion of the top surface and at least a portion of the sidewalls of the fin; and
filling the opening with a conductive material to form a contact with one of the source/drain regions, the contact in connection with the top surface and sidewalls of the fin.
2. The method of claim 1 , wherein forming an opening includes exposing a portion of at least two sidewalls.
3. The method of claim 1 , wherein forming an opening includes exposing a portion of at least three sidewalls.
4. The method of claim 1 , wherein the inter-layer dielectric imparts a stress to the area of the fin between the source/drain regions.
5. The method of claim 1 , further comprising forming a contact etch stop layer over the non-planar transistor prior to forming an inter-layer dielectric, the contact etch stop layer imparting a stress to an area of the fin between the source/drain regions.
6. The method of claim 1 , further comprising forming the source/drain regions at least in part through segregated doping.
7. The method of claim 1 , further comprising forming a metal silicide over the source/drain regions.
8. The method of claim 1 , further comprising forming a metal layer over the source/drain regions.
9. A method for forming a semiconductor device, the method comprising:
forming a conductive region over a substrate, the conductive region comprising a first region with a first lattice constant, a second region with a second lattice constant different from the first lattice constant, and a third region opposite the second region from the first region, the third region having the first lattice constant;
forming an inter-layer dielectric over the conductive region;
forming an opening through the inter-layer dielectric to expose at least three surfaces of the conductive region, the at least three surfaces forming an exposed conductive region; and
filling the opening with a conductive material to form a contact with the exposed conductive region.
10. The method of claim 9 , wherein the forming an opening includes exposing at least four surfaces of the conductive region.
11. The method of claim 9 , wherein the forming a conductive region further comprises:
providing a conductive layer over the substrate, the conductive layer having the second region;
removing a first section and a second section of the conductive layer on opposing sides of the second region; and
forming the first region and the third region.
12. The method of claim 9 , further comprising stressing the second region.
13. The method of claim 12 , wherein the inter-layer dielectric stresses the second region.
14. The method of claim 12 , wherein the stressing the second region includes forming a contact etch stop layer over the conductive region prior to the forming the inter-layer dielectric.
15. The method of claim 9 , further comprising forming silicide regions over at least a portion of the conductive region prior to the forming the inter-layer dielectric.
16. A method of forming a semiconductor device, the method comprising:
forming a conductive fin over a substrate, the conductive fin comprising an upper surface and sidewalls, the sidewalls having a first height, the conductive fin also comprising a first section, a second section, and a third section interposed between the first section and the second section, the third section having a different conductivity than the first section and the second section;
forming an inter-layer dielectric over the conductive fin;
forming at least one aperture through the inter-layer dielectric to expose at least a portion of the upper surface and at least a portion of the sidewalls, the forming the at least one aperture only exposing a portion of the first height of the sidewalls; and
filling the at least one aperture with a conductive material to form at least one contact to the conductive fin, the at least one contact being in physical connection with the upper surface and at least a portion of two or more of the sidewalls.
17. The method of claim 16 , further comprising forming a contact etch stop layer over the conductive fin prior to forming an inter-layer dielectric, the contact etch stop layer imparting a stress to the third section.
18. The method of claim 16 , wherein the forming the conductive fin further comprises:
providing a conductive layer, the conductive layer comprising the third section;
removing a first portion and a second portion of the conductive layer around the third section; and
growing the first section and the second section adjacent to the third section.
19. The method of claim 18 , wherein the growing the first section and the second section further comprises growing the first section and the second section to have a different lattice constant than the third section.
20. The method of claim 16 , wherein the forming the at least one aperture comprises exposing at least four surfaces of the conductive fin.