FinFETs with different fin height and EPI height setting
An integrated circuit structure includes a first semiconductor strip, first isolation regions on opposite sides of the first semiconductor strip, and a first epitaxy strip overlapping the first semiconductor strip. A top portion of the first epitaxy strip is over a first top surface of the first isolation regions. The structure further includes a second semiconductor strip, wherein the first and the second semiconductor strips are formed of the same semiconductor material. Second isolation regions are on opposite sides of the second semiconductor strip. A second epitaxy strip overlaps the second semiconductor strip. A top portion of the second epitaxy strip is over a second top surface of the second isolation regions. The first epitaxy strip and the second epitaxy strip are formed of different semiconductor materials. A bottom surface of the first epitaxy strip is lower than a bottom surface of the second epitaxy strip.
1. An integrated circuit structure comprising:
a first semiconductor strip;
first isolation regions on opposite sides of the first semiconductor strip;
a first epitaxy strip overlapping the first semiconductor strip, wherein a top portion of the first epitaxy strip is over a first top surface of the first isolation regions;
a second semiconductor strip, wherein the first semiconductor strip and the second semiconductor strip are formed of a same semiconductor material;
second isolation regions on opposite sides of the second semiconductor strip; and
a second epitaxy strip overlapping the second semiconductor strip, wherein a top portion of the second epitaxy strip is over a second top surface of the second isolation regions, wherein the first epitaxy strip and the second epitaxy strip are formed of different semiconductor materials, and wherein a first bottom surface of the first epitaxy strip is lower than a second bottom surface of the second epitaxy strip.
2. The integrated circuit structure of claim 1 , wherein the first top surface of the first isolation regions is lower than the second top surface of the second isolation regions.
3. The integrated circuit structure of claim 1 , wherein the first top surface of the first isolation regions is coplanar with the second top surface of the second isolation regions.
4. The integrated circuit structure of claim 1 , wherein the first epitaxy strip has a first bandgap, the second epitaxy strip has a second bandgap different from the first bandgap, and the first semiconductor strip and the second semiconductor strip have a third bandgap different from the first bandgap and the second bandgap.
5. The integrated circuit structure of claim 4 , wherein the first bandgap is greater than the third bandgap, and the second bandgap is smaller than the third bandgap, wherein the bottom surface of the first epitaxy strip is lower than the first top surface of the first isolation regions, and the bottom surface of the second epitaxy strip is higher than the second top surface of the second isolation regions.
6. The integrated circuit structure of claim 4 , wherein the first bandgap and the second bandgap are both smaller than the third bandgap, wherein the first bottom surface of the first epitaxy strip is higher than the first top surface of the first isolation regions, and the second bottom surface of the second epitaxy strip is higher than the second top surface of the second isolation regions.
7. The integrated circuit structure of claim 4 , wherein the first bandgap and the second bandgap are both higher than the third bandgap, wherein the first bottom surface of the first epitaxy strip is lower than the first top surface of the first isolation regions, and the second bottom surface of the second epitaxy strip is lower than the second top surface of the second isolation regions.
8. An integrated circuit structure comprising:
a first semiconductor strip;
first isolation regions on opposite sides of the first semiconductor strip, wherein the first isolation regions have first top surfaces;
a first epitaxy strip overlapping the first semiconductor strip, wherein a top portion of the first epitaxy strip is over the first top surfaces of the first isolation regions;
a second semiconductor strip, wherein the first semiconductor strip and the second semiconductor strip are formed of a same semiconductor material;
second isolation regions on opposite sides of the second semiconductor strip, wherein the second isolation regions have second top surfaces higher than the first top surfaces; and
a second epitaxy strip overlapping the second semiconductor strip, wherein a top portion of the second epitaxy strip is over the second top surfaces of the second isolation regions.
9. The integrated circuit structure of claim 8 , wherein the first epitaxy strip and the second epitaxy strip are formed of different semiconductor materials.
10. The integrated circuit structure of claim 8 , wherein a first bottom surface of the first epitaxy strip is lower than a second bottom surface of the second epitaxy strip.
11. The integrated circuit structure of claim 8 , wherein the first epitaxy strip is configured as a channel region of a p-type Fin Field-Effect Transistor (FinFET), and wherein the second epitaxy strip is configured as a channel region of an n-type FinFET.
12. The integrated circuit structure of claim 8 , wherein the first epitaxy strip has a first bandgap, the second epitaxy strip has a second bandgap different from the first bandgap, and the first semiconductor strip and the second semiconductor strip have a third bandgap different from the first bandgap and the second bandgap.
13. The integrated circuit structure of claim 12 , wherein the first bandgap is higher than the third bandgap, and wherein the first top surfaces of the first isolation regions are higher than a first bottom surface of the first epitaxy strip.
14. The integrated circuit structure of claim 12 , wherein the first bandgap is lower than the third bandgap, and wherein the first top surfaces of the first isolation regions are lower than a first bottom surface of the first epitaxy strip.
15. An integrated circuit structure comprising:
a first semiconductor strip and a second semiconductor strip, wherein the first semiconductor strip and the second semiconductor strip are formed of a same semiconductor material having a first bandgap;
first isolation regions on opposite sides of the first semiconductor strip;
a first epitaxy strip overlying the first semiconductor strip and having a second bandgap greater than the first bandgap, wherein a first interface between the first epitaxy strip and the first semiconductor strip is lower than first top surfaces of the first isolation regions;
second isolation regions on opposite sides of the second semiconductor strip; and
a second epitaxy strip overlying the second semiconductor strip and having a third bandgap lower than the first bandgap, wherein a second interface between the second epitaxy strip and the second semiconductor strip is higher than second top surfaces of the second isolation regions.
16. The integrated circuit structure of claim 15 , wherein the first top surfaces of the first isolation regions are not coplanar with the second top surfaces of the second isolation regions.
17. The integrated circuit structure of claim 15 , wherein the first top surfaces of the first isolation regions are coplanar with the second top surfaces of the second isolation regions.
18. The integrated circuit structure of claim 15 , wherein the first interface is lower than the second interface.
19. The integrated circuit structure of claim 15 , wherein the first epitaxy strip and the second epitaxy strip are comprised in a p-type Fin Field-Effect Transistor (FinFET) and an n-type FinFET, respectively.
20. The integrated circuit structure of claim 15 further comprising a semiconductor substrate underlying the first and the second isolation regions, wherein the semiconductor substrate is formed of a same semiconductor material as the first semiconductor strip and the second semiconductor strip.