Low-cost and ultra-fine integrated circuit packaging technique
View Patent ↗A semiconductor package structure and the methods for forming the same are provided. The semiconductor package structure includes an interposer; a first plurality of bonding pads on a side of the interposer; a semiconductor chip; and a second plurality of bonding pads on a side of the semiconductor chip. The first and the second plurality of bonding pads are bonded through metal-to-metal bonds.
1. A semiconductor package structure comprising:
an interposer;
a first plurality of bonding pads on a side of the interposer;
a semiconductor chip; and
a second plurality of bonding pads on a side of the semiconductor chip, wherein the first and the second plurality of bonding pads are bonded through metal-to-metal bonds.
2. The semiconductor package structure of claim 1 , wherein the interposer comprises silicon.
3. The semiconductor package structure of claim 1 , wherein the interposer comprises a plurality of through-silicon vias.
4. The semiconductor package structure of claim 3 , wherein the first plurality of bonding pads has a first pitch, and wherein the through-silicon vias have a second pitch greater than the first pitch.
5. The semiconductor package structure of claim 1 , wherein the first pitch is less than about 130 μm.
6. The semiconductor package structure of claim 1 , wherein each of the first and the second plurality of bonding pads comprises a material selected from the group consisting essentially of copper, aluminum, and combinations thereof.
7. The semiconductor package structure of claim 1 further comprising an interfacial bonding layer between each of the first plurality of bonding pads and a respective bonding pad in the second plurality of bonding pads.
8. The semiconductor package structure of claim 7 , wherein the interfacial bonding layer has a thickness of less than about 10 μm.
9. The semiconductor package structure of claim 8 , wherein the interfacial bonding layer comprises solder.
10. The semiconductor package structure of claim 1 further comprising interfacial bonding materials on sidewalls of the first and the second plurality of bonding pads, wherein each of the first plurality of bonding pads is in physical contact with a respective bonding pad in the second plurality of bonding pads.
11. A semiconductor package structure comprising:
an interposer;
a first plurality of bonding pads on a side of the interposer;
a multi-chip semiconductor structure having at least a first chip and a second chip; and
a second plurality of bonding pads on a side of the first chip, wherein bonds between the first and the second plurality of bonding pads are bonded through metal-to-metal bonds.
12. The semiconductor package structure of claim 11 , wherein the first and the second bonding pads have a pitch of less than about 50 μm.
13. The semiconductor package structure of claim 12 , wherein the pitch is less than about 5 μm.
14. The semiconductor package structure of claim 11 , wherein the first and the second plurality of bonding pads each comprise a material selected from the group consisting essentially of copper, aluminum, and combinations thereof, and wherein the bonds between the first and the second plurality of bonding pads further comprise thin interfacial bonding layers.
15. A semiconductor package structure comprising:
an interposer comprising:
a silicon-containing substrate;
a plurality of through-silicon vias in the silicon-containing substrate;
a first plurality of bonding pads connected to the plurality of through-silicon vias, wherein the first plurality of bonding pads are on a first side of the interposer, and wherein the first plurality of the bonding pads has a first pitch; and
a second plurality of bonding pads on a second side of the interposer opposite to the first side, wherein the second plurality of bonding pads has a second pitch less than the first pitch; and
a semiconductor chip comprising a third plurality of bonding pads bonded to the second plurality of bonding pads, wherein the second and the third plurality of bonding pads are bonded through metal-to-metal bonds.
16. The semiconductor package structure of claim 15 , wherein the second and the third plurality of bonding pads are bonded through direct copper-to-copper bonds.
17. The semiconductor package structure of claim 15 further comprising an interfacial bonding layer between each pair of the first and the second plurality of bonding pads, wherein the interfacial bonding layer has a thickness of less then about 1 μm.
18. The semiconductor package structure of claim 15 further comprising an additional semiconductor chip bonded onto the semiconductor chip, wherein the semiconductor chip comprises through-silicon vias.
19. The semiconductor package structure of claim 15 , wherein the interposer comprises passive devices formed in dielectric layers overlying the silicon-containing substrate.
20. The semiconductor package structure of claim 19 , wherein the interposer further comprises active devices formed in the silicon interposer.