Wafer backside interconnect structure connected to TSVs

1. An integrated circuit structure comprising:

a semiconductor substrate having a front surface and a back surface opposite the front surface;

a conductive via in the semiconductor substrate;

a first metal feature extending from the back surface of the semiconductor substrate into the semiconductor substrate and contacting the conductive via, wherein a surface of the first metal feature opposite the conductive via is substantially level with the back surface of the semiconductor substrate, wherein the conductive via is disposed between the first metal feature and the front surface of the semiconductor substrate in a plane, wherein the plane is perpendicular to the front surface of the semiconductor substrate;

a bump overlying and electrically connected to the first metal feature; and

a second metal feature formed between the first metal feature and the bump, wherein the second metal feature comprises a dual damascene structure.

2. The integrated circuit structure of claim 1 , further comprising a dielectric layer on the back surface of the semiconductor substrate, wherein the second metal feature is disposed in the dielectric layer.

3. The integrated circuit structure of claim 1 , wherein all horizontal dimensions of the first metal feature are greater than respective horizontal dimensions of the conductive via.

4. The integrated circuit structure of claim 1 , wherein the first metal feature comprises:

a conductive barrier layer contacting the conductive via; and

a copper-containing metallic material over the conductive barrier layer.

5. The integrated circuit structure of claim 1 further comprising an active device at the front surface of the semiconductor substrate, and wherein the back surface is opposite the front surface of the semiconductor substrate.

6. The integrated circuit structure of claim 1 , further comprising an additional metal feature extending from the back surface of the semiconductor substrate into the semiconductor substrate, wherein the additional metal feature does not extend through the semiconductor substrate.

7. An integrated circuit structure comprising:

a semiconductor substrate;

an active device on a front surface of the semiconductor substrate;

a through-substrate via (TSV) extending at least partially through the semiconductor substrate;

a first metal feature at a back surface of the semiconductor substrate and electrically connected to the TSV, wherein all horizontal dimensions of the first metal feature are greater than respective horizontal dimensions of the TSV, and wherein the back surface is opposite the front surface of the semiconductor substrate, wherein a surface of the first metal feature opposite the TSV is substantially level with the back surface of the semiconductor substrate; and

a second metal feature on the back surface of the semiconductor substrate, wherein the second metal feature comprises a dual damascene structure.

8. The integrated circuit structure of claim 7 , wherein the first metal feature extends from the back surface of the semiconductor substrate into the semiconductor substrate.

9. The integrated circuit structure of claim 7 , further comprising a metal line in the semiconductor substrate.

10. The integrated circuit structure of claim 7 , further comprising a bump electrically connected to the first metal feature.

11. The integrated circuit structure of claim 7 , wherein the second metal feature contacts a top surface of the first metal feature.

12. The integrated circuit structure of claim 7 , wherein the second metal feature is disposed in a dielectric layer, and wherein the integrated circuit structure further comprises an etch stop layer disposed between the semiconductor substrate and the dielectric layer.

13. An integrated circuit structure comprising:

a semiconductor substrate comprising an active device at a front surface of the semiconductor substrate;

an interconnect structure at the front surface of the semiconductor substrate;

a conductive via in the semiconductor substrate;

a first metal feature in the semiconductor substrate and electrically connected to the conductive via, wherein the first metal feature extends from a back surface of the semiconductor substrate into the semiconductor substrate, wherein the back surface is opposite the front surface of the semiconductor substrate;

a second metal feature adjacent the first metal feature extending from the back surface of the semiconductor substrate into the semiconductor substrate, wherein the second metal feature is a redistribution line, wherein the second metal feature is disposed outside of a region of the semiconductor substrate, wherein the region of the semiconductor substrate is bounded by a first line extending along a first sidewall of the conductive via and a second line extending along a second sidewall of the conductive via opposite the first sidewall, and wherein a portion of the semiconductor substrate is disposed between the first metal feature and the second metal feature; and

a third metal feature on the first metal feature, wherein the third metal feature comprises a dual damascene structure.

14. The integrated circuit structure of claim 13 , wherein the conductive via extends at least partially through the interconnect structure.

15. The integrated circuit structure of claim 13 further comprising a bump on the first metal feature.

16. The integrated circuit structure of claim 1 further comprising a redistribution line extending from the back surface of the semiconductor substrate into the semiconductor substrate.

17. The integrated circuit structure of claim 16 wherein lateral surfaces of the redistribution line and the first metal feature are substantially level.

18. The integrated circuit structure of claim 1 , wherein a transistor is disposed at the front surface of the semiconductor substrate.