Semiconductor device

1. A semiconductor integrated circuit apparatus comprising:

a periodic signal generation circuit connected with N logical circuits, wherein the N is a natural number, outputting a periodic signal; and

a reset circuit outputting a reset signal initializing according to outputs from a first stage logic circuit to N−1th logic circuit among the N logic circuits,

wherein the reset circuit comprises:

a plurality of NOR gate input with at least two of the output signals among the output signals from the first stage logic circuit to the N−1th logic circuit; and

an AND gate input with outputs from the plurality of NOR gate.

2. A semiconductor integrated circuit, comprising:

a shift register having a plurality of registers including a first stage register coupled to an input of the shift register, a final stage register coupled to an output of the shift register, and other registers coupled between the first stage register and the final stage register, each of the registers being respectively responsive to a clock signal to transfer an input signal at the input of the shift register towards the output of the shift register; and

a reset circuit coupled to receive output signals from each of the registers except for the final stage register to set another input signal for the shift register in response selectively to the first stage register and the other registers among the registers in the shift register.

3. The semiconductor integrated circuit according to claim 2 , wherein the another input signal has a same signal level with the input signal.

4. The semiconductor integrated circuit according to claim 2 further comprising an internal circuit block different from the reset circuit and different from the shift register, the output of the shift register being coupled to the internal circuit block, wherein a clock input of the first stage register is coupled with a clock input of the final stage register whereas an input of the first stage register is separate from an output of the final stage register.

5. The semiconductor integrated circuit according to claim 2 , wherein the reset circuit includes a NOR gate coupled to an output port of one of the plurality of registers included in the shift register, and an AND gate coupled to an output port of the NOR gate.

6. The semiconductor integrated circuit according to claim 5 , wherein

the reset circuit further includes another NOR gate coupled to an output port of another one of said plurality of registers included in the shift register, and

the AND gate is coupled to an output port of the another NOR gate.

7. A semiconductor integrated circuit, comprising:

a shift register including a first stage register, final stage register, and other registers connected between the first stage register and the final stage register, and capable of shifting an input data from the first stage register to the final stage register via the other registers, each of the first register and the final register, and each of the other registers receiving a synchronized clock signal; and

a reset circuit outputting a reset signal to set another input data to the shift register in response to an output signal from the shift register,

wherein the final stage register does not set a data to the first stage register in the shift register.

8. A semiconductor integrated circuit, comprising:

a function block to which an input data is set and capable of performing a predetermined operation to the input data in response to a clock signal; and

a reset circuit outputting a reset signal to set another input data to the function block in response to a phenomenon generated in the function block caused by an abnormal reduction of an amplitude of the clock signal.

9. The semiconductor integrated circuit according to claim 8 , wherein the function block is a shift register including a first stage register, final stage register, and other registers connected between the first stage register and the final stage register, and capable of shifting an input data from the first stage register to the final stage register via the other registers, each of the first register and the final register, and each of the other registers receiving a clock signal.