IP Library Granted Patent US 7,716,410
Granted Patent B2
US 7,716,410 · App. 11/584,550 · Granted May 11, 2010

Information device including main processing circuit, interface circuit, and microcomputer

Assignee: Renesas Technology Corp.
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Quick Facts
Patent No.
US 7,716,410
App. No.
11/584,550
Granted
May 11, 2010
Kind
B2
Abstract

An information device includes a main processing circuit for executing signal processing related to a main function in the information device, a main microcomputer for controlling the main processing circuit, a receiver circuit for interfacing with the outside of the information device, and an interface microcomputer for controlling the receiver circuit, the interface microcomputer being provided separately from the main microcomputer.

Claims (19)

1. An information device packaged in a single package, comprising:

a main function unit including a main processing circuit for executing signal processing related to a main function in said information device and a first microcomputer for controlling said main processing circuit by executing a first firmware program; and

an interface function unit including a first interface circuit for receiving data from an exterior device located outside of said information device to provide to said main processing circuit, a second interface circuit for performing an authentication operation with the exterior device, and a second microcomputer provided separately from said first microcomputer for controlling said first interface circuit, and a memory for storing a second firmware program for controlling said first interface circuit,

wherein said main function unit executes said signal processing based on said received data,

wherein said second microcomputer downloads said second firmware from said memory by executing a download program, and controls said authentication operation of said second interface circuit,

wherein said interface function unit is a product of a single-chip process that is separate from said main function unit,

wherein said second microcomputer has the function of communicating with said first microcomputer, and

wherein said first microcomputer resets said second microcomputer via said function of communicating in accordance with a state of receiving data to provide to said main function unit.

2. The information device according to claim 1 ,

wherein said first interface circuit and said second microcomputer are connected to each other by using a parallel interface.

3. The information device according to claim 1 ,

wherein said first interface circuit receives an externally inputted video signal and an externally inputted audio signal corresponding to said video signal to output said video signal and said audio signal in parallel, said information device further comprising a lip-sync circuit for adjusting the timing between said video signal and said audio signal outputted in parallel from said first interface circuit, and said lip-sync circuit being subjected to a product of the single-chip process together with said first interface circuit and said second microcomputer.

4. The information device according to claim 1 , wherein said first interface circuit includes a receiver circuit for receiving an external signal to output said external signal, and a transmitter circuit for outputting a signal outputted from said receiver circuit to said exterior device.

5. The information device according to claim 1 , further comprising:

a plurality of input ports for receiving respective external signals; and

a switch circuit for selecting one of the external signals inputted to said plurality of input ports to output a selected signal to said first interface circuit, said switch circuit being subjected to a product of the single-chip process together with said first interface circuit and said second microcomputer.

6. The information device according to claim 1 , wherein said first interface circuit receives an encrypted signal inputted from said exterior device, decrypts said encrypted signal, and outputs the decrypted signal, said information device further comprising a watermarking circuit for embedding a watermark into a signal outputted from said first interface circuit to output the resultant signal, and said watermarking circuit being subjected to a product of the single-chip process together with said first interface circuit and said second microcomputer.

7. The information device according to claim 1 ,

wherein said first interface circuit is an interface circuit conforming to HDMI (High-Definition Multimedia Interface).

Assignments (4)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
MERGER Recorded Aug 27, 2010
From: RENESAS TECHNOLOGY CORPORATION
To: NEC ELECTRONICS CORPORATION
Reel/Frame 024892/0877 →
CHANGE OF NAME Recorded Aug 27, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 024944/0437 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 29, 2006
From: NAGANO, HIDEO; MURAMATSU, KIKUO; KOYAMA, MASAYUKI; ANDO, TOMOKO; HIGASHIDA, MOTOKI; ARAKAWA, TAKAHIKO; HATAKENAKA, MAKOTO
To: RENESAS TECHNOLOGY CORP.
Reel/Frame 018562/0276 →
Priority Claims (1)
JP 2005-310939 · Oct 26, 2005 · national
Continuity (1)
Related Publication 20070091122A1 · Apr 26, 2007