Efficient transistor structure
An integrated circuit comprises a first drain region having a generally rectangular shape. First, second, third and fourth source regions have a generally rectangular shape and that are arranged adjacent to sides of the first drain region. A gate region is arranged between the first, second, third and fourth source regions and the first drain region. First, second, third and fourth substrate contact regions that are arranged adjacent to corners of the first drain region.
1. An integrated circuit comprising:
a first drain region having a generally rectangular shape;
first, second, third and fourth source regions that have a generally rectangular shape and that are arranged adjacent to sides of said first drain region;
a gate region that is arranged between said first, second, third and fourth source regions and said first drain region; and
first, second, third and fourth substrate contact regions that are arranged adjacent to corners of said first drain region.
2. The integrated circuit of claim 1 wherein said first, second, third and fourth source regions have a length that is substantially equal to a length of said first drain region.
3. The integrated circuit of claim 1 wherein said first, second, third and fourth source regions have a width that is less than a width of said first drain region.
4. The integrated circuit of claim 3 wherein said width of said first, second, third and fourth source regions is approximately one-half the width of said first drain region.
5. The integrated circuit of claim 1 further comprising
a second drain region having a generally rectangular shape and having one side that is arranged adjacent to said first source region; and
fifth, sixth and seventh source regions that have a generally rectangular shape and that are arranged adjacent to other sides of said second drain region.
6. The integrated circuit of claim 5 further comprising a gate region that is arranged between said first, fifth, sixth and seventh source regions and said second drain region.
7. The integrated circuit of claim 6 further comprising fifth and sixth substrate contact regions that are arranged adjacent to corners of said second drain region.
8. The integrated circuit of claim 1 wherein said integrated circuit includes laterally-diffused MOSFET transistors.
9. The integrated circuit of claim 1 further comprising B source contacts in each of said first, second, third and fourth source regions, where B is an integer greater than one, and a drain contact region.
10. The integrated circuit of claim 9 wherein said drain contact region includes first and second drain contacts that have an area D and said B source contacts have an area A and wherein said area D is greater than or equal to 2*B*A.
11. A method for providing an integrated circuit comprising:
providing a first drain region having a generally rectangular shape;
arranging sides of first, second, third and fourth source regions, which have a generally rectangular shape, adjacent to sides of said first drain region;
arranging a gate region between said first, second, third and fourth source regions and said first drain region; and
arranging first, second, third and fourth substrate contact regions adjacent to corners of said first drain region.
12. The method of claim 11 wherein said first, second, third and fourth source regions have a length that is substantially equal to a length of said first drain region.
13. The method of claim 11 wherein said first, second, third and fourth source regions have a width that is less than a width of said first drain region.
14. The method of claim 11 wherein said width of said first, second, third and fourth source regions is approximately one-half the width of said first drain region.
15. The method of claim 11 further comprising
arranging one side of a second drain region, which has a generally rectangular shape, adjacent to said first source region; and
arranging fifth, sixth and seventh source regions, which have a generally rectangular shape, adjacent to other sides of said second drain region.
16. The method of claim 15 further comprising arranging a gate region between said first, fifth, sixth and seventh source regions and said second drain region.
17. The method of claim 16 further comprising arranging fifth and sixth substrate contact regions adjacent to corners of said second drain region.
18. The method of claim 11 wherein said integrated circuit includes laterally-diffused MOSFET transistors.
19. The method of claim 11 further comprising arranging B source contacts in each of said first, second, third and fourth source regions, where B is an integer greater than one, and a drain contact region in said drain region.
20. The method of claim 19 wherein said drain contact region includes first and second drain contacts that have an area D and said B source contacts have an area A and wherein said area D is greater than or equal to 2*B*A.