Semiconductor memory device
View Patent ↗Disclosed is a semiconductor memory device comprising a memory cell array block, and a circuit region arranged with the memory cell array block along a first direction. The circuit region comprises a first region and a second region arranged with the first region along the first direction. The first region is provided with a first circuit and a second circuit which are aligned in a second direction perpendicular to the first direction. The second region is provided with a plurality of third circuits which are aligned in the second direction.
1. A semiconductor memory device comprising:
a memory cell array block; and
a circuit region arranged with the memory cell array block along a first direction, wherein the circuit region comprises a first region and a second region arranged with the first region along the first direction, the first region comprises a first circuit and a second circuit which are aligned in a second direction perpendicular to the first direction and which have functions different from each other, the second region comprises a plurality of third circuits which are aligned in the second direction and which have functions same as each other.
2. The semiconductor memory device according to claim 1 , further comprising:
a first line elongated along the second direction and electrically coupled to the first circuit; and
a second line elongated along the second direction and electrically coupled to the second circuit, the second line being separated from the first line.
3. The semiconductor memory device according to claim 2 , wherein the first line and the second line are aligned with each other in the second direction.
4. The semiconductor memory device according to claim 2 , further comprising:
a third line which is electrically coupled to the first line to supply a first voltage for the first circuit; and
a fourth line which is different from the third line and is electrically coupled to the second line to supply a second voltage for the second circuit.
5. The semiconductor memory device according to claim 1 , wherein the circuit region is a sense amplifier region where a plurality of sense amplifiers are disposed.
6. The semiconductor memory device according to claim 1 , wherein the circuit region is a sub word region where a plurality of sub word drivers are disposed.
7. The semiconductor memory device according to claim 1 , wherein the circuit region is an x decoder region where a plurality of X decoders are disposed.
8. The semiconductor memory device according to claim 1 , wherein the circuit region is a y decoder region where a plurality of Y decoders are disposed.